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toshiba original cmos 32-bit microcontroller tlcs-900/h1 series tmp92cy23fg tmp92cy23dfg tmp92cd23afg TMP92CD23ADFG semiconductor company
preface thank you very much for making us e of toshiba microcomputer lsis. before use this lsi, refer the se ction, ?notes and restrictions?.
tmp92cy23/cd23a 2009-08-28 92cy23-1 cmos 32-bit microcontrollers tmp92cy23fg/tmp92cy23dfg/t mp92cd23afg/TMP92CD23ADFG 1. outline and device characteristics the tmp92cy23/cd23a are a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. the tmp92cy23/cd23a has a high-performance cpu (900/h1 cpu) and various built-in i/os. tmp92cy23fg, tmp92cy23fg, tmp92cd23afg and TMP92CD23ADFG are housed in a 100-pin flat package. product name ram rom package lqfp100-p-1414-0.50f tmp92cy23fg tmp92cy23dfg 16k byte 256k byte qfp-p-1420-0.65a lqfp100-p-1414-0.50f tmp92cd23afg TMP92CD23ADFG 32k byte 512k byte qfp-p-1420-0.65a device characteristics are as follows: (1) cpu: 32-bit cpu (900/h1 cpu) ? compatible with 900/l1 instruction code ? 16 mbytes of linear address space ? general-purpose register and register banks ? micro dma: 8 channels (250 ns/4 bytes at f sys = 20 mhz, best case) (2) minimum instruction execution time: 50 ns (at f sys = 20 mhz) (3) external memory expansion ? expandable up to 16 mbytes (shared program/data area) ? can simultaneously support 8- or 16-bit width external data bus ??? dynamic data bus sizing ? separate bus system (4) memory controller ? chip select output: 4 channels (5) 8-bit timers: 6 channels (6) 16-bit timers: 2 channels (7) general-purpose serial interface: 3 channels ? uart/synchronous mode: 3 channels (channel 0 , 1 and 2) ? irda ver.1.0 (115 kbps) mode selectable: 3 channels (channel 0 , 1 and 2) (8) serial bus interface: 2 channels ? i 2 c bus mode ? clock synchronous mode (9) high speed serial interface: 1 channels note: this circuit is not built into tmp92cy23. (10) 10-bit ad converter: 12 channels (11) watchdog timer (12) special timer for clock
tmp92cy23/cd23a 2009-08-28 92cy23-2 (13) key-on wake up (only for halt release):8 channels (14) program patch logic: 8 banks (15) interrupts: tmp92cy23: 50 interrupts, tmp92cd23a: 51 interrupts ? 9 cpu interrupts: software interrupt instruction and illegal instruction ? 32 internal interrupts (tmp92cy23), 33 internal interrupts (tmp92cd23a) : seven selectable priority levels ? 9 external interrupts (int0 to int7 and nmi ): seven selectable priority levels (int0 to int7 selectable edge or level interrupt) (16) input/output ports: 84 pins (17) standby function ? three halt modes: idle2 (programmable), idle1, stop (18) clock controller ? clock doubler (pll) ? clock gear function: select high-frequency clock fc to fc/16 ? special timer for clock (fs = 32.768 khz) (19) operating voltage ? v cc = 3.0 v to 3.6 v (fc max = 40 mhz f osch max = 10mhz(tmp92cd23a)) (20) package ? 100-pin qfp: lqfp100-p-1414-0.50f (tmp92cy23fg/tmp92cd23afg) qfp100-p-1420-0.65a (t mp92cy23dfg/TMP92CD23ADFG)
tmp92cy23/cd23a 2009-08-28 92cy23-3 figure 1.1 tmp92cy23/cd23a block diagram ( ): initial function after reset note: this circuit is not built into tmp92cy23. dvss [4] dvcc [4] x x2 h-osc clock gear pll l-osc avss/vrefl avcc/vrefh port g (pg0)an0/ki0 (pg1)an1/ki1 (pg2)an2/ki2 (pg3)an3/ki3 (pg4)an4/ki4 (pg5)an5/ki5 (pg6)an6/ki6 (pg7)an7/ki7 (pl0)an8 (pl1)an9 (pl2)an10 (pl3)an11/ adtrg port l 10-bit 12ch ad converter key-on wake up (pn0)sck0 (pn1)so0/sda0 (pn2)si0/scl0 (pn3)sck1 (pn4)so1/sda1 (pn5)si1/scl1 port n serial bus i/f (ch.0) serial bus i/f (ch.1) (pf0)txd0 (pf1)rxd0 (pf2)sclk0/ 0cts /clk (pf3)hsso/txd1 (pf4)hssi/rxd1 (pf5)hsclk/sclk1/ 1cts port f serial i/o (ch.0) serial i/o (ch.1) (pd0)tb0out0/int4 (pd1)tb1in0/int5 (pd2)tb1in1/txd2/int6 (pd3)tb1out0/rxd2/int7 (pd4)tb1out1/sclk2/ 2cts port d (pc0)ta0in (pc1)int1 (pc2)int2 (pc3)int3 port c 16-bit timer (tmrb1) 16-bit timer (tmrb0) serial i/o (ch.2) interrupt controller nmi mode controller reset a m0 a m1 special timer for clock watchdog timer (wdt) 32-kb ram 512-kb rom program patch logic 8-banks tlcs-900/h1 cpu ix i y iz sp lh ed cb a w f sr 32bit pc xw a xbc xde xhl xix xiy xiz xsp port 0 d0 to d7 (p00 to p07) port 1 d8 to d15 (p10 to p17) port 4 a 0 to a7 (p40 to p47) port 5 a 8 to a15 (p50 to p57) port 6 a 16 to a23 (p60 to p67) 8-bit timer (tmra5) 8-bit timer (tmra4) 8-bit timer (tmra3) 8-bit timer (tmra2) 8-bit timer (tmra1) 8-bit timer (tmra0) port 8 port 7 0 cs /ta1out (p80) 1 cs /ta3out (p81) 2cs (p82) 3cs / wait /ta5out (p83) xt2 (p77) xt1 (p76) int0 (p74) srlub (p73) srllb (p72) srwr (p71) rd (p70) memory controller (4-blocks) high speed serial i/o (note)
tmp92cy23/cd23a 2009-08-28 92cy23-4 2. pin assignment and functions the assignment of input/output pins for the tmp92cy23/cd23a, their names and functions are as follows: 2.1 pin assignment diagram figure 2.1.1 shows the pin assignment of the tmp92cy23fg/tmp92cd23afg. a vss/vrefl tmp92cy23fg tmp92cd23afg lqfp100 topview 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 a vcc/vr efh p c1/int1 pc2/in t2 pc3/in t3 pf0/txd0 pf1/rxd0 pf2/sclk0/c ts0/cl k pf3/txd1/hsso pf4/rxd1/hssi pc0/ta0in pf5/sclk1/cts1/hscl k pn0/sck0 pn1/so0/sda0 pn 2/si0/scl0 pn4/so1/sda1 pn 5/si1/scl1 pn3/sck1 pd0/tb0out0/int4 dvss p74/int0 p00/d0 p02/d2 x1 dvs s x2 a m1 pd2/tb1in1/int6/txd2 pd1/tb1in0/int5 p83/cs3/wait/ta5ou t p82/cs2 p81/cs1/ta3ou t p80/cs0/ta1out p67/a23 p66/a22 p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p 47/a7 p46/a 6 p 45/a5 p44/a4 p43/a3 p42/a 2 p41/a1 p40/a0 dvcc nmi dvss p17/d15 p16/d14 p15/d13 p14/d12 p13 /d11 p12/d1 0 p11/d9 p10/d8 p07/d 7 p06/d6 p05/d 5 p04/d4 p03/d3 p g7 /an7/ki7 p g2/an2/ki2 p l0/an8 pg6/an6/ki 6 p g5/an5/ki5 p g4/an4/ki4 p g3/an3/ki3 pl2/an10 p g1/an1/ki1 pg0/an0/ki0 dvs s p d4/tb1out1/sclk2/cts2 pd3/tb1out0/rxd2/int 7 p73/srl u b p72/srll b p7 1/srwr p70/r d dvc c p76/xt1 p77/xt2 a m0 rese t p01/d1 dvcc pl1 /an9 dvcc pl3/an11/adtrg note: hsso, hssi and hsclk functions are not built into tmp92cy23. figure 2.1.1 pin assignment diagram (100-pin lqfp)
tmp92cy23/cd23a 2009-08-28 92cy23-5 figure 2.1.2 shows the pin assignment of the tmp92cy2 3dfg/TMP92CD23ADFG. tmp92cy23dfg TMP92CD23ADFG qfp100 topview 35 40 45 55 60 65 70 75 p 77/xt2 p g1/ an1 /ki 1 p g0/an0/ki0 a vss/vr ef l a vcc/vrefh p c0/ta0in pc1/int1 p c2/int2 p c3/int3 p f0/txd0 pf1/rxd0 p f2/sclk0/cts0/clk p f3/txd1/hss o p f4/ rxd1/hssi pf5/sclk1/cts1/hsclk pn0 /sck0 p n1/so0/sda0 pn2/si0/scl 0 pn4/so1/sda1 pn5/si1/scl1 pn3/sck1 p d0/tb0out0/int4 dvs s p74/int 0 dvcc p 00/d0 p01/d1 p02/d2 p03/d 3 p04/d 4 p05/d5 p06/d6 p07/d7 p10/d8 p11/d9 p12/d10 p13/d11 p14/d12 p15/d13 p16/d14 p17/d15 dvss nmi dvcc p40/a0 p41 / a1 p42 / a2 p 43 / a3 p44/a4 p45 / a5 p46 / a6 p 47/a7 p 50/a8 p51/a9 p52/a10 p53/a11 p 54/a12 p55/a13 p56/a14 p57/a15 p60/a16 p61/a17 p62/a18 p 63/a19 p 64/a20 p65/a21 p66/a22 p 67/a23 p80/cs0/ta1out p81/cs1/ta3ou t p 82/cs2 p83/cs3/wait/ta5 ou t pd1/tb1in0/int 5 pd2/tb1in1/int6/txd 2 a m1 x2 dvss x1 dvcc reset a m0 p76/xt1 dvcc p70/ r d p71/srw r p72/sr ll b p73/srlub pd3/tb1out0/rxd2/int7 pd4/tb1out1/sclk2/cts2 dvss pl3/an 11/adtrg pl2/an10 pl1/an9 p l0/an8 pg7/an7/ki7 pg6/an6/ki6 pg5/an5/ki5 pg4/an4/ki4 pg3/an3/ki3 pg2/an2/ki2 1 10 5 15 20 25 30 50 80 85 90 95 10 0 note: hsso, hssi and hsclk functions are not built into tmp92cy23. figure 2.1.2 pin assignment diagram (100-pin qfp)
tmp92cy23/cd23a 2009-08-28 92cy23-6 2.2 pin names and functions the following table shows the names and functions of the input/output pins. table 2.2.1 pin names and functions (1/3) pin name number of pin i/o function p00 to p07 d0 to d7 8 i/o i/o port 0: i/o port input or output specifiable in units of bits data: data bus 0 to 7 p10 to p17 d8 to d15 8 i/o i/o port 1: i/o port input or output specifiable in units of bits data: data bus 8 to 15 p40 to p47 a0 to a7 8 i/o output port 4: i/o port input or output specifiable in units of bits address: address bus 0 to 7 p50 to p57 a8 to a15 8 i/o output port 5: i/o port input or output specifiable in units of bits address: address bus 8 to 15 p60 to p67 a16 to a23 8 i/o output port 6: i/o port input or output specifiable in units of bits address: address bus 16 to 23 p70 rd 1 i/o output port 70: i/o port (schmitt input, with pull-up resistor) read: outputs strobe signal for read external memory. p71 srwr 1 i/o output port 71: i/o port (schmitt input, with pull-up resistor) write enable for sram: strobe signal for wiritng data. p72 srllb 1 i/o output port 72: i/o port (schmitt input, with pull-up resistor) data enable for sram on pins d0 to d7 p73 srlub 1 i/o output port 73: i/o port (schmitt input, with pull-up resistor) data enable for sram on pins d8 to d15 p74 int0 1 input input port 74: input port (schmitt input) interrupt request pin 0 : interrupt request pin with programmable level/rising/falling edge p76 xt1 1 i/o input port 76: i/o port (open drain output) low-frequency oscillator connection input pins p77 xt2 1 i/o output port 77: i/o port (open drain output) low-frequency oscillator connection output pins p80 0cs ta1out 1 output output output port 80: output port chip select 0: outputs ?low? when address is within specified address area 8-bit timer 1 output: output pin of 8-bit timer tmra0 or tmra1 p81 1cs ta3out 1 output output output port 81: output port chip select 1: outputs ?low? when address is within specified address area 8-bit timer 3 output: output pin of 8-bit timer tmra2 or tmra3 p82 2cs 1 output output port 82: output port chip select 2: outputs ?low? when address is within specified address area p83 3cs ta5out wait 1 i/o output output input port 83: i/o port (schmitt input) chip select 3: outputs ?low? when address is within specified address area 8-bit timer 5 output: output pin of 8-bit timer tmra4 or tmra5 wait: signal used to request cpu bus wait pc0 ta0in 1 input input port c0: input port (schmitt input) 8-bit timer 0 input: input pin of 8-bit timer tmra0 pc1 int1 1 input input port c1: input port (schmitt input) interrupt request pin 1 : interrupt request pin with programmable level/rising/falling edge pc2 int2 1 input input port c2: input port (schmitt input) interrupt request pin 2 : interrupt request pin with programmable level/rising/falling edge pc3 int3 1 input input port c3: input port (schmitt input) interrupt request pin 3 : interrupt request pin with programmable level/rising/falling edge
tmp92cy23/cd23a 2009-08-28 92cy23-7 table 2.2.2 pin names and functions (2/3) pin name number of pin i/o function pd0 tb0out0 int4 1 i/o output input port d0: i/o port (schmitt input) 16-bit timer 0 output 0: output pin of 16-bit timer tmrb0 interrupt request pin 4 : interrupt request pin with programmable level/rising/falling edge pd1 tb1in0 int5 1 input input input port d1: input port (schmitt input) 16-bit timer 1 input 0: input of count/capture trigger in 16-bit timer tmrb1 interrupt request pin 5 : interrupt request pin with programmable level/rising/falling edge pd2 tb1in1 txd2 int6 1 i/o input output input port d2: i/o port (schmitt input) 16-bit timer 1 input 1: input of count/capture trigger in 16-bit timer tmrb1 serial 2 send data: open drain output programmable interrupt request pin 6 : interrupt request pin with programmable level/rising/falling edge pd3 tb1out0 rxd2 int7 1 i/o output input input port d3: i/o port (schmitt input) 16-bit timer 1 output 0: output pin of 16-bit timer tmrb1 serial 2 receive data interrupt request pin 7 : interrupt request pin with programmable level/rising/falling edge pd4 tb1out1 sclk2 2cts 1 i/o output i/o input port d4: i/o port (schmitt input) 16-bit timer 1 output 1: output pin of 16-bit timer tmrb1 serial 2 clock i/o serial 2 data send enable (clear to send) pf0 txd0 1 i/o output port f0: i/o port (schmitt input) serial 0 send data: open drain output programmable pf1 rxd0 1 i/o input port f1: i/o port (schmitt input) serial 0 receive data pf2 sclk0 0cts clk 1 i/o i/o input output port f2: i/o port (schmitt input) serial 0 clock i/o serial 0 data send enable (clear to send) clock: system clock output pf3 txd1 hsso 1 i/o output output port f3: i/o port (schmitt input) serial 1 send data: open drain output programmable high speed serial send data (note) pf4 rxd1 hssi 1 i/o input input port f4: i/o port (schmitt input) serial 1 receive data high speed serial receive data (note) pf5 sclk1 1cts hsclk 1 i/o i/o input output port f5: i/o port (schmitt input) serial 1 clock i/o serial 1 data send enable (clear to send) high speed serial clock output (note) pg0 to pg7 an0 to an7 ki0 to ki7 8 input port g: input port (schmitt input) analog input 0 to 7: pin used to input to ad conveter key input 0 to 7: pin used for key-on wakeup 0 to 7 pl0 to pl3 an8 to an11 adtrg 4 input port l: input port (schmitt input) analog input 8 to 11: pin used for input to a/d conveter a/d trigger: signal used for request a/d start (shared with pl3) note: hsso, hssi and hsclk functions are not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-8 table 2.2.3 pin names and functions (3/3) pin name number of pin i/o function pn0 sck0 1 i/o i/o port n0: i/o port (schmitt input) serial bus interface 0 clock i/o data at sio mode pn1 so0 sda0 1 i/o output i/o port n1: i/o port (schmitt input, open drain output) serial bus interface 0 send data at sio mode serial bus interface 0 send/receive data at i 2 c mode pn2 si0 scl0 1 i/o input i/o port n2: i/o port (schmitt input, open drain output) serial bus interface 0 receive data at sio mode serial bus interface 0 clock i/o data at i 2 c mode pn3 sck1 1 i/o i/o port n3: i/o port (schmitt input) serial bus interface 1 clock i/o data at sio mode pn4 so1 sda1 1 i/o output i/o port n4: i/o port (schmitt input, open drain output) serial bus interface 1 send data at sio mode serial bus interface 1 send/receive data at i 2 c mode pn5 si1 scl1 1 i/o input i/o port n5: i/o port (schmitt input, open drain output) serial bus interface 1 receive data at sio mode serial bus interface 1 clock i/o data at i 2 c mode nmi 1 input non-maskable interrupt request pin: interrupt request pin with programmable falling edge level or with both edge levels programmable (schmitt input) am0, am1 2 input operation mode: fixed to am1 = ?1? and am0 = ?1? x1 / x2 2 i/o high-frequency oscillator connection i/o pins reset 1 input reset: intializes tmp92cy23/cd23a (s chmitt input, with pull-up resistor) avcc / vrefh 1 input pin used for both power supply pin for ad converter and standard power supply for ad converter (h) avss / vrefl 1 input pin used for both gnd pin for ad converter (0 v) and standard power supply pin for ad converter (l) dvcc 4 ? power supply pins (all dvcc pins should be connected to the power supply pin) dvss 4 ? gnd pins (0 v) (all dvss pins shold be connected to gnd(0v))
tmp92cy23/cd23a 2009-08-28 92cy23-9 3. operation this section describes the basic components, functions and operation of the tmp92cy23/ cd23a. 3.1 cpu the tmp92cy23/cd23a contains an advanced high-speed 32-bit cpu (tlcs-900/h1 cpu) 3.1.1 cpu outline the tlcs-900/h1 cpu is a high-speed, high-performance cpu based on the tlcs-900/l1 cpu. the tlcs-900/h1 cpu has an expanded 32-bit internal data bus to process instructions more quickly. the following is an outline of the cpu: table 3.1.1 tmp92cy23/cd23a outline parameter tmp92cy23/cd23a width of cpu address bus 24 bits width of cpu data bus 32 bits internal operating frequency max 20 mhz minimum bus cycle 1-clock access (50 ns at f sys = 20mhz) internal ram 32-bit 1-clock access internal rom 32-bit interleave 2-1-1-1-clock access internal i/o 8-bit 2-clock access external sram, masked rom 8- or 16-bit 2-clock access (waits can be inserted) minimum instruction execution cycle 1-clock (50 ns at f sys =20mhz) conditional jump 2-clock (100 ns at f sys =20mhz) instruction queue buffer 12 bytes instruction set compatible with tlcs-900/l1 (ldx instruction is deleted) cpu mode maximum mode only micro dma 8 channels
tmp92cy23/cd23a 2009-08-28 92cy23-10 3.1.2 reset operation when resetting the tmp92cy23/cd23a, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input low for at least 20 system clocks (64 s at fc = 10 mhz). at reset, since the clock doubler (pll) is by passed and the clock-gear is set to 1/16, the system clock operates at 312.5 khz (fc = 10 mhz). when the reset has been accepted, the cpu performs the following: ? sets the program counter (pc) as follows in accordance with the reset vector stored at address ffff00h to ffff02h: pc<7:0> data in location ffff00h pc<15:8> data in location ffff01h pc<23:16> data in location ffff02h ? sets the stack pointer (xsp) to 00000000h. ? sets bits of the status register (sr) to 111 (thereby setting the interrupt level mask register to level 7). ? clears bits of the status register to 00 (there by selecting register bank 0). when the reset is released, the cpu starts executing instructions according to the program counter settings. cpu internal regist ers not mentioned above do not change when the reset is released. when the reset is accepted, the cpu sets internal i/o, ports and ot her pins as follows. ? initializes the internal i/o registers. ? sets the port pins, including the pins that also act as internal i/o, to general-purpose input or output port mode. a reset input terminal becomes ?high?, if reset release is carried out, a built-in flashrom warm-up circuit (notes) will start operation, and internal reset will be canceled after the end of the circuit of operation. memory controller operation cannot be ensured until the power supply becomes stable after power-on reset. external ram data provided before turning on the tmp92cy23/cd23a may be corrupted because the control signals are unstable until the power supply beco mes stable after power-on reset. note: although this product is a maskrom product, in order to consider as the same operation as a flashrom product, built-in flashrom warm-up ti me enters. the warm-up time of build-in flashrom into becomes it as follows. at f osch = 10 mhz 409.6 s (2 12 / f osch )
tmp92cy23/cd23a 2009-08-28 92cy23-11 figure 3.1.1 shows the example of operating the reset timing of tmp92cy23/cd23a. figure 3.1.1 powe r on re set timing example 3.1.3 setting of am0 and am1 set am1 and am0 pins as shown in table 3.1.2 according to system usage. table 3.1.2 operation mod e setup table mode setup input pin operation mode reset am1 am0 internal rom starting 1 1 high-frequency oscillation stabilized time + 20 system clock 0 s (min) vcc (3.3 v) reset
tmp92cy23/cd23a 2009-08-28 92cy23-12 3.2 memory map figure 3.2.2 show the memory maps of the tmp92cy23, and figure 3.2.2 show the memory maps of the tmp92cd23a respectively. figure 3.2.1 tmp92cy23 memory map external memory external memory internal i/o (8 kbytes) internal ram (16 kbytes) direct area (n) 64-kbytes area (nn) 16-mbytes area (r) ( ?r) (r +) (r + r8/16) (r + d8/16) (nnn) 000000h 000100h 002000h 006000h f00000h f10000h ffff00h ffffffh ( = internal area) provisional emulator control (64 kbytes) 010000h (note 1) (note 2) vector table (256 bytes) internal rom (256 kbytes) fc0000h
tmp92cy23/cd23a 2009-08-28 92cy23-13 figure 3.2.2 tmp92cd23a memory map note 1: the provisional emulator control area, mapped f00000h to f0ffffh after reset, is for emulator use and so is not availab le. when emulator srwr signal and rd signal are asserted, this area is access ed. ensure external memory is used. note 2: do not use the last 16-byte area (fffff0h to ffffffh). this area is reserved for an emulator. external memory external memory internal i/o (8 kbytes) internal ram (32 kbytes) direct area (n) 64-kbytes area (nn) 16-mbytes area (r) ( ?r) (r +) (r + r8/16) (r + d8/16) (nnn) 000000h 000100h 002000h 00a000h f00000h f10000h ffff00h ffffffh ( = internal area) provisional emulator control (64 kbytes) 010000h (note 1) (note 2) vector table (256 bytes) internal rom (512 kbytes) f80000h
tmp92cy23/cd23a 2009-08-28 92cy23-14 3.3 clock function and stand-by function the tmp92cy23/cd23a contains (1) clock ge ar, (2) clock doubler (pll), (3) stand-by controller and (4) noise reduction circuits. they are used for low power, low noise systems. this chapter is organized as follows: 3.3.1 block diagram of system clock 3.3.2 sfr 3.3.3 system clock controller 3.3.4 clock doubler (pll) 3.3.5 noise reduction circuits 3.3.6 stand-by controller
tmp92cy23/cd23a 2009-08-28 92cy23-15 the clock operating modes are as follows: (a) single clock mode (x1, x2 pins only), (b) dual clock mode (x1, x2, xt1 and xt2 pins) and (c) tr iple clock mode (x1, x2, xt1 and xt2 pins and pll). figure 3.3.1 shows a transition figure. reset (f osch /32) release reset instruction interrupt stop mode (stops all circuits) normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) (a) single clock mode transition figure (b) dual clock mode transition figure slow mode (fs/2) reset (f osch /32) release reset normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) idle2 mode (i/o operate) idle1 mode (operate only oscillator) instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction instruction interrupt interrupt instruction interrupt stop mode (stops all circuits) instruction interrupt stop mode (stops all circuits) using pll note reset (f osch /32) release reset normal mode (f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate only oscillator) stop mode (stops all circuits) slow mode (fs/2) normal mode (4 f osch /gear value/2) idle2 mode (i/o operate) idle1 mode (operate oscillator and pll) idle2 mode (i/o operate) idle1 mode (operate only oscillator) (c) triple clock mode transition figure instruction instruction interrupt interrupt instruction instruction instruction interrupt note instruction instruction interrupt instruction instruction interrupt interrupt interrupt interrupt instruction instruction instruction interrupt note 1: it is not possible to control pll in slow mode when shifting from slow mode to normal mode with use of pll. (pll start up/stop/change write to pllcr0, pllcr1 register) note 2: when shifting from normal mode with use of pll to normal mode, execute the following setting in the same order. 1) change cpu clock (pllcr0 ?0?) 2) stop pll circuit (pllcr1 ?0?) note 3: it is not possible to shift from normal mode with use of pll to stop mode directly. normal mode should be set once before shifting to stop mode. (stop the high-frequency oscillator after stopping pll.) figure 3.3.1 system clock block diagram the clock frequency input from th e x1 and x2 pins is called f osch and the clock frequency input from the xt1 and xt2 pins is called fs. the clock frequency selected by syscr1 is called the clock f fph . the system clock f sys is defined as the divided clock of f fph , and one cycle of f sys is defined as one state.
tmp92cy23/cd23a 2009-08-28 92cy23-16 3.3.1 block diagram of system clock tmra0 to 5,tmr b0 t o 1 f sys cpu rom interrupt controller ram ad c prescaler t0 sio0 to sio2 special timer for clock f s prescaler i/o ports c lock-gear syscr1 selector fs f osch low-frequency oscillator xt1 xt2 syscr0 warm-up timer (h igh/low-frequency oscillator) sy scr 0 sy scr 2 x1 x2 clock doubler (pll) f pl l = f osch 4 2 16 4 fc/ 1 6 fc/8 fc/4 fc/2 f c pl lcr0 syscr1 2 4 f fph f sys 2 t0 fs t s ys cr0 high-frequency oscillator 8 lock up timer (pll) pllcr1, pllcr0 wdt sbi0 to sbi1 prescaler t hsc (note) note: this circuit is not built into tmp92cy23. figure 3.3.2 block diag ram of system clock frequency of external oscillator is 6 to 10mhz. don?t connect oscillator more than 10mhz. (tmp92cd23a only)
tmp92cy23/cd23a 2009-08-28 92cy23-17 3.3.2 sfr 7 6 5 4 3 2 1 0 bit symbol xen xten wuef read/write r/w r/w reset state 1 0 0 function high- frequency oscillator (f osch ) 0: stop 1: oscillation low- frequency oscillator (fs) 0: stop 1: oscillation warm-up timer 0: write don?t care 1: write start timer 0: read end warm-up 1: read do not end warm-up 7 6 5 4 3 2 1 0 bit symbol sysck gear2 gear1 gear0 read/write r / w reset state 0 1 0 0 function select system clock 0: fc 1: fs select gear value of high-frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: reserved 110: reserved 111: reserved 7 6 5 4 3 2 1 0 bit symbol ? wuptm1 wuptm0 haltm1 haltm0 drve read/write r/w r/w r/w reset state 0 1 0 1 1 0 function always write ?0? warm-up timer 00: reserved 01: 2 8 /input frequency 10: 2 14 /input frequency 11: 2 16 /input frequency halt mode 00: reserved 01: stop mode 10: idle1 mode 11: idle2 mode 1: the inside of stop mode also drives a pin note 1: the unassigned registers, syscr0, syscr0, syscr1, and syscr2 are read as undefined value. note 2: low-frequency oscillator is enabled on reset. figure 3.3.3 sfr for system clock syscr0 (10e0h) syscr1 (10e1h) syscr2 (10e2h)
tmp92cy23/cd23a 2009-08-28 92cy23-18 7 6 5 4 3 2 1 0 bit symbol protect extin(note) ? drvoscl read/write r r/w reset state 0 0 1 1 emccr0 (10e3h) function protect flag 0: off 1: on 1: external clock always write ?1? fs oscillator driver ability 1: normal 0: weak note: this register is a register for tmp92cy23. there is no in tmp92cd23a. please refer to the following for the register for tmp92cd23a. 7 6 5 4 3 2 1 0 bit symbol protect ? ? drvoscl read/write r r/w reset state 0 0 1 1 function protect flag 0: off 1: on always write ?0? always write ?1? fs oscillator driver ability 1: normal 0: weak note: this register is a register for tmp92cd23a. note1: when restarting the oscillator from the stop oscillation state (e.g. restar ting the oscillator in stop mode), set emccr0 = ?1?. note2: do not write emccr0 = ?1? when using external resonator. 7 6 5 4 3 2 1 0 bit symbol read/write reset state function bit symbol read/write reset state function switch the protect on/off by writing the following to 1st-key, 2nd-key 1st-key: write in sequence emccr1 = 5ah, emccr2 = a5h 2nd-key: write in sequence emccr1 = a5h, emccr2 = 5ah figure 3.3.4 sfr for system clock emccr0 (10e3h) emccr1 (10e4h) emccr2 (10e5h)
tmp92cy23/cd23a 2009-08-28 92cy23-19 7 6 5 4 3 2 1 0 bit symbol fcsel lupfg read/write r/w r reset state 0 0 function select fc clock 0: f osch 1: f pll lock up timer status flag 0: not end 1: end note: ensure that the logic of pllcr0 is different from 900/l1?s dfm. 7 6 5 4 3 2 1 0 bit symbol pllon read/write r / w reset state 0 function control on/off 0: off 1: on figure 3.3.5 sfr for pll pllcr0 (10e8h) pllcr1 (10e9h)
tmp92cy23/cd23a 2009-08-28 92cy23-20 3.3.3 system clock controller the system clock controller gene rates the system clock signal (f sys ) for the cpu core and internal i/o. it contains two oscillation circu its and a clock gear circuit for high-frequency (fc) operation. the register syscr1 changes the system clock to either fc or fs, syscr0 and syscr0 control enab ling and disabling of each oscillator, and syscr1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). these functions can reduce the power consumption of the equipment in which the device is installed. the combination of settings = ?1?, = ?0? and = ?100? will cause the system clock (f sys ) to be set to fc/32 (fc/16 1/2) after reset. for example, f sys is set to 0.3125 mhz when the 10 mhz oscillator is connected to the x1 and x2 pins. (1) switching from normal mode to slow mode when the resonator is connected to the x1 and x2 pins, or to the xt1 and xt2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. the warm-up time can be sele cted using syscr2. this warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. table 3.3.1 shows the warm-up time. note 1: when using an oscillator (othe r than a resonator) with stable oscillation, a warm-up timer is not needed. note 2: the warm-up timer is operated by an oscillation clo ck. hence, there may be some variation in warm-up time. table 3.3.1 warm-up times at f osch = 10 mhz, fs = 32.768 khz warm-up time syscr2 change to normal mode change to slow mode 01 (2 8 /frequency) 25.6 ( s) 7.8 (ms) 10 (2 14 /frequency) 1.638 (ms) 500 (ms) 11 (2 16 /frequency) 6.554 (ms) 2000 (ms)
tmp92cy23/cd23a 2009-08-28 92cy23-21 example 1: setting the clock changing from high-frequency (fc) to low-frequency (fs). syscr0 equ 10e0h syscr1 equ 10e1h syscr2 equ 10e2h ld (syscr2), 0 x 1 1 ? ? x ? b ; sets warm-up time to 2 16 /fs. set 6, (syscr0) ; enables low-frequency oscillation. set 2, (syscr0) ; clears and starts warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detects stopping of warm-up timer. set 3, (syscr1) ; changes f sys from fc to fs. res 7, (syscr0) ; disables high-frequency oscillation. x: don?t care, ?: no change enables low-frequency clears and starts warm-up timer chages f sys from fc to fs end of warm-up timer disabiles high-frequency fc x1, x2 pins xt1, xt2 pins warm-up timer system clock f sys end of warm-up timer fs counts up by f sys counts up by fs
tmp92cy23/cd23a 2009-08-28 92cy23-22 example 2: setting the clock changing from low-frequency (fs) to high-frequency (fc). syscr0 equ 10e0h syscr1 equ 10e1h syscr2 equ 10e2h ld (syscr2), 0 x 1 0 ? ? x ? b ; sets warm-up time to 2 14 /fc. set 7, (syscr0) ; enables high-frequency oscillation. set 2, (syscr0) ; clears and starts warm-up timer. wup: bit 2, (syscr0) ; jr nz, wup ; detects stopping of warm-up timer. res 3, (syscr1) ; changes f sys from fs to fc. res 6, (syscr0) ; disables low-frequency oscillation. x: don?t care, ?: no change counts up by f sys counts up by fc disables low-frequency enables high-frequency clears and starts warm-up time r changes f sys from fs to fc end of warm-up time r x1, x2 pins xt1, xt2 pins warm-up timer system clock f sys end of warm-up timer fc fs
tmp92cy23/cd23a 2009-08-28 92cy23-23 (2) clock gear controller f fph is set according to the contents of the clock gear select register syscr1 to either fc, fc /2, fc/4, fc/8 or fc/16. using the clock gear to select a lower value of f fph reduces power consumption. example 3: changing to a high-frequency gear syscr1 equ 10e1h ld (syscr1), xxxx0001b ; changes f sys to fc/2. x: don?t care (high-speed clock gear changing) to change the clock gear, write the register value to the syscr1 register.it is necessary for the warm-up time to elapse before the change occurs after writing the register value. there is the possibility that the instruction following the clock gear changing instruction is executed by the clock gear before changing.to execute the instruction following the clock gear switching instructio n by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). example: syscr1 equ 10e1h ld (syscr1), xxxx0010b ; changes f sys to fc/4. ld (dummy), 00h ; dummy instruction instruction to be executed after clock gear has changed
tmp92cy23/cd23a 2009-08-28 92cy23-24 3.3.4 clock doubler (pll) pll outputs the f pll clock signal, which is four times as fast as f osch . a low-speed-frequency oscillator can be used, even though the internal clock is high-frequency. a reset initializes pll to stop status, so setting to pllcr0, pllcr1 register is needed before use. as with an oscillator, this circuit requires time to stabilize. this is called the lock up time and it is measured by a 16-stage binary counter. lock up time is about 1.6 ms at f osch = 10 mhz. note 1: input frequency range for pll the input frequency range (high-frequency oscillation) for pll is as follows: f osch = 6 to 10 mhz (v cc = 3.0 to 3.6 v) note 2: pllcr0 the logic of pllcr0 is different from 900/l1?s dfm. exercise care in determining the end of lock up time. the following is an example of settings for pll starting and pll stopping. example 1: pll starting pllcr0 equ 10e8h pllcr1 equ 10e9h ld (pllcr1), 1 x x x x xx x b ; enables pll operation and starts lock up . lup: bit 5, (pllcr0) ; jr z, lup ; detects end of lock up. ld (pllcr0), x 1 x x x xx x b ; changes fc from 10 mhz to 40 mhz. x: don?t care counts up by f osch changes from 10 mhz to 40 mhz starts pll operation and starts lock up pll output: f pll lock up timer system clock f sys a fter lock u p during lock up lock up ends
tmp92cy23/cd23a 2009-08-28 92cy23-25 example 2: pll stopping pllcr0 equ 10e8h pllcr1 equ 10e9h ld (pllcr0), x0xxxxxxb ; changes fc from 40 mhz to10 mhz. ld (pllcr1), 0xxxxxxxb ; stop pll. x: don?t care changes from 40 mhz to 10 mhz pll output: f pll system clock f sys stops pll operation
tmp92cy23/cd23a 2009-08-28 92cy23-26 limitations on the use of pll 1. it is not possible to execute pll enable/disable control in the slow mode (fs) (writing to pllcr0 and pllcr1). pll should be controlled in the normal mode. 2. when stopping pll operation during pll use, execute the following settings in the same order. ld (pllcr0), 00h ; change the clock f pll to f osch ld (pllcr1), 00h ; pll stop 3. when stopping the high-frequency oscillator during pll use, stop pll before stopping the high-frequency oscillator. examples of settings are shown below: (1) start up/change control (ok) low-frequency oscillator operation mode (fs) (high-frequency oscillator stop) high-frequency oscillator start up high-frequency oscillator operation mode (f osch ) pll start up pll use mode (f pll ) ld (syscr0), 1 1 ? ? ? 1 ? ? b ; high-frequency oscillator start/warm-up start wup: bit 2, (syscr0) ; jr nz, wup ; check for warm-up end flag ld (syscr1), ? ? ? ? 0 ? ? ? b ; change the system clock fs to f osch ld (pllcr1), 1 ? ? ? ? ? ? ? b ; pll start-up/lock up start lup: bit 5, (pllcr0) ; jr z, lup ; check for lock up end flag ld (pllcr0), ? 1 ? ? ? ? ? ? b ; change the system clock f osch to f pll (ok) low-frequency oscillator operation mode (fs) (high-frequency oscillator operate) high-frequency oscillator operation mode (f osch ) pll start up pll use mode (f pll ) ld (syscr1), ? ? ? ? 0 ? ? ? b ; change the system clock fs to f osch ld (pllcr1), 1 ? ? ? ? ? ? ? b ; pll start-up/lock up start lup: bit 5, (pllcr0) ; jr z, lup ; check for lock up end flag ld (pllcr0), ? 1 ? ? ? ? ? ? b ; change the system clock f osch to f pll (error) low-frequency oscillator operation mode (fs) (high-frequency oscillator stop) high-frequency oscillator start up pll start up pll use mode (f pll ) ld (syscr0), 1 1 ? ? ? 1 ? ? b ; high-frequency oscillator start/warm-up start wup: bit 2, (syscr0) ; jr nz, wup ; check for warm-up end flag ld (pllcr1), 1 ? ? ? ? ? ? ? b ; pll start-up/lock up start lup: bit 5, (pllcr0) ; jr z, lup ; check for lock up end flag ld (pllcr0), ? 1 ? ? ? ? ? ? b ; change the internal clock f osch to f pll ld (syscr1), ? ? ? ? 0 ? ? ? b ; change the system clock fs to f pll
tmp92cy23/cd23a 2009-08-28 92cy23-27 (2) change/stop control (ok) pll use mode (f pll ) high-frequency oscillator operation mode (f osch ) pll stop low-frequency oscillator operation mode (fs) high-frequency oscillator stop ld (pllcr0), ? 0 ? ? ? ? ? ? b ; change the system clock f pll to f osch ld (pllcr1), 0 ? ? ? ? ? ? ? b ; pll stop ld (syscr1), ? ? ? ? 1 ? ? ? b ; change the system clock f osch to fs ld (syscr0), 0 ? ? ? ? ? ? ? b ; high-frequency oscillator stop (error) pll use mode (f pll ) low-frequency oscillator operation mode (fs) pll stop high-frequency oscillator stop ld (syscr1), ? ? ? ? 1 ? ? ? b ; change the system clock f pll to fs ld (pllcr0), ? 0 ? ? ? ? ? ? b ; change the internal clock (f c ) f pll to f osch ld (pllcr1), 0 ? ? ? ? ? ? ? b ; pll stop ld (syscr0), 0 ? ? ? ? ? ? ? b ; high-frequency oscillator stop (ok) pll use mode (f pll ) set the stop mode high-frequency oscillator operation mode (f osch ) pll stop halt (high-frequency oscillator stop) ld (syscr2), ? ? ? ? 01 ? ? b ; set the stop mode (this command can be executed before use of pll) ld (pllcr0), ? 0 ? ? ? ? ? ? b ; change the system clock f pll to f osch ld (pllcr1), 0 ? ? ? ? ? ? ? b ; pll stop halt ; shift to stop mode ( error) pll use mode (f pll ) set the stop mode halt (high-frequency oscillator stop) ld (syscr2), ? ? ? ? 01 ? ? b ; set the stop mode (this command can execute before use of pll) halt ; shift to stop mode
tmp92cy23/cd23a 2009-08-28 92cy23-28 3.3.5 noise reduction circuits noise reduction circuits are built-in, allowing implementation of the following features. (1) reduced drivability for low-frequency oscillator (2) reduced drivability for low-frequency oscillator (note) (3) sfr protection of register contents note: this function can use only tmp92cy23. these functions need a setup by emccr0, emccr1, and emccr2 register. (1) reduced drivability for low-frequency oscillator (purpose) reduces noise and power for oscillator when a resonator is used. (block diagram) (setting method) the drive ability of the oscillator is reduced by writing ?0? to the emccr0 register. at reset, is initialized to ?1? and the oscillator starts oscillation by normal drivability when the power-supply is on. f s enable oscillation emccr0 xt1 pin xt2 pin c1 c2 resonator
tmp92cy23/cd23a 2009-08-28 92cy23-29 (2) single drive for high-frequency oscillator (note) (purpose) remove the need for twin drives and prevent operational errors caused by noise input to x2 pin when an external oscillator is used . note: this function can use only tmp92cy23. (block diagram) ( setting method) the oscillator is disabled and starts operation as buffer by writing ?1? to emccr0 register. x2 pi n?s output is always ?1?. at reset, is initialized to ?0?. note: do not write emccr0 = ?1? when using external resonator. f osch enable oscillation emccr0 x1 pin x2 pin
tmp92cy23/cd23a 2009-08-28 92cy23-30 (2) runaway prevention using sfr protection register (purpose) prevention of program runaway caused by introduction of noise. write operations to a specified sfr are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (memory controller) which prevent fetch operations. runaway error handling is also facilitated by intp0 interruption. specified sfr list 1. memory controller b0csl/h, b1csl/h, b2csl/h, b3csl/h, bexcsl/h msar0, msar1, msar2, msar3, mamr0, mamr1, mamr2, mamr3, pmemcr 2. clock gear syscr0, syscr1, syscr2, emccr0 4. pll pllcr0, pllcr1 (operation explanation) execute and release of protection (write operation to specified sfr) becomes possible by setting up a double key to emccr1 and emccr2 registers. (double key) 1st key: writes in sequence, 5ah at emccr1 and a5h at emccr2 2nd key: writes in sequence, a5h at emccr1 and 5ah at emccr2 protection state can be confirmed by reading emccr0. at reset, protection becomes off. intp0 interruption also occurs when a write operation to the specified sfr is executed with protection in the on state.
tmp92cy23/cd23a 2009-08-28 92cy23-31 3.3.6 stand-by controller (1) halt modes and port drive register when the halt instruction is executed, the operating mode switches to idle2, idle1 or stop mode, depending on the contents of the syscr2 register. the subsequent actions performed in each mode are as follows: 1. idle2: only the cpu halts. the internal i/o is available to select operation during idle2 mode by setting the following register. table 3.3.2 shows the register se ttin g op eration during idle2 mode . table 3.3.2 sfr setting operation during idle2 mode internal i/o sfr tmra01 ta01run tmra23 ta23run tmra45 ta45run tmrb0 tb0run tmrb1 tb1run sio0 sc0mod1 sio1 sc1mod1 sio2 sc2mod1 ad converter admod1 wdt wdmod sbi0 sbi0br0 sbi1 sbi1br0 2. idle1: only the oscillator and the special timer for clock continue to operate. 3. stop: all internal circuits stop operating. the operation of each of the different halt modes is described in table 3.3.3. table 3.3.3 i/o oper ation during halt modes halt mode idle2 idle1 stop syscr2 11 10 01 cpu stop i/o ports the state at the time of "halt" instruction execution is held. table 3.3.7 and table 3.3.8 references tmra, tmrb sio, sbi ad converter wdt available to select operation block interrupt controller stop hsc (note) block special timer for clock operate operate note: this circuit is not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-32 (2) how to release the halt mode these halt states can be released by resetting or requesting an interrupt. the halt release sources are determined by the combination of the states of the interrupt mask register and the halt modes. the details for releasing the halt status are shown in table 3.3.4. release by in terrupt requestin g the halt mode release method depends on the status of the enabled interrupt .when the interrupt request level set before executing the halt instruction exceeds the value of the interrupt mask register, the interrupt is processed depending on its status after the halt mode is released, and the cpu status executing the instruction that follows the halt instruction. when the interrupt request level set before executing the halt instruction is less than the value of the interrupt mask register, halt mode release is not executed. (in non-maskable interrupts, interrupt proces sing is processed after releasing the halt mode regardless of the value of the mask register.) however only for int0 to int7, intrtc interrupts, even if the inte rrupt request level set before executing the halt instruction is less than the value of the interrupt mask register, halt mode release is executed. in this case, the interrupt is processed, and the cpu starts executing the instruction following the halt instruction, but the interrupt request flag is held at ?1?. release by resetting release of all halt statuses is executed by resetting. when the stop mode is released by reset, it is necessary to allow enough resetting time (see table 3.3.5) for operation of the oscilla tor t o stabilize. when releasing the halt mode by resetting, the internal ram data keeps the state before the halt instruction is executed. however the other settings contents are initialized. (releasing due to interrupts keeps the state before the halt instruction is executed.)
tmp92cy23/cd23a 2009-08-28 92cy23-33 table 3.3.4 source of halt state cl earance and halt clearance operation status of received interrupt interrupt enabled ( interrupt level) (interrupt mask) interrupt disabled ( interrupt level) < (interrupt mask) halt mode idle2 idle1 stop idle2 idle1 stop nmi ? ? ?* 1 ? ? ? intwdt ? ? ? ? int0 to int4, int7 (note 1) ? ? ? * 1 * 1 int5,int6 (port) (note 1) ? ? ? * 1 * 1 int5,int6 (tmrb1) ? intta0 to intta5 ? intb00, inttb01, inttb10, inttb11, inttbo0, inttbo1 ? intrx0 to intrx2, inttx0 to inttx2 ? intad ? kwi ? ? ? * 1 intrtc ? ? intsbe0 to intsbe1 ? interrupt inthsc (note4) ? source of halt state clearance reset initialize lsi ? : after clearing the halt mode, cpu starts interrupt processing. : after clearing the halt mode, cpu resumes executing starting from the instruction following the halt instruction. : cannot be used to release the halt mode. ? : the priority level (interrupt request level) of non-m askable interrupts is fixed to 7, the highest priority level. this combination is not available. : since kwi does not have a function as interr uption, this combination does not exist. * 1: release of the halt mode is exec uted after warm-up time has elapsed. note 1: when the halt mode is cleared by an int0 to 7 interrupt of the level mode in the interrupt enabled status, hold level ?h? until starting interrupt processing. if level ?l ? is set before holding level ?l?, interrupt processing is correctly started. note 2: although a kwi can cancel all halt mode st ates, the function as inte rruption does not have it. note 3: specify the hscsel register when selecting inttx1 or inthsc interrupt with the same interrupt factor. note4: the inthsc interrupt is not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-34 example: releasing idle1 mode an int0 interrupt clears the halt st ate when the device is in idle1 mode. address 8200h ld (p7fc), 10h ; sets p74 to int0 interrupt. 8203h ld (iimc3), 00h ; selects int0 interrupt rising edge. 8206h ld (iimc2), 00h ; selects int0 interrupt edge 8209h ld (inte01), 06h sets int0 interrupt level to 6. 820bh ei 5 ; sets interrupt level to 5 for cpu. 820eh ld (syscr2), 28h ; sets halt mode to idle1 mode. 820fh halt ; halts cpu. int0 int0 interrupt routine reti 8210h ld xx, xx
tmp92cy23/cd23a 2009-08-28 92cy23-35 (3) operation 1. idle2 mode in idle2 mode only specific internal i/o operations, as designated by the idle2 setting register, can take place. instruction execution by the cpu stops. figure 3.3.6 illustrates an example of the timing for clearance of the idle2 mo de halt state by an inte rrupt. figure 3.3.6 timing chart for idle2 mo de halt state cleared by interrupt 2. idle1 mode in idle1 mode, only the internal oscillator and special timer for clock continue to operate. the system clock stops. in the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it. figure 3.3.7 illustrates the timing for clearance of the idle1 mode halt state by an interrupt. figure 3.3.7 timing cha rt for idle1 mo de halt state cleared by interrupt data data idle2 mode x1 a0 to a23 d0 to d15 rd wr interrupt for release halt data data idle1 mode x1 a0 to a23 d0 to d15 rd wr interrupt for release halt
tmp92cy23/cd23a 2009-08-28 92cy23-36 3. stop mode when stop mode is selected, all internal circuits stop, including the internal oscillator. after stop mode has been cleared system clock output starts when the warm-up time by the counter for a warm-u p of internal oscillator and built-in flashrom warm-up time. the example of a setting of the warm-up time at the time of stop mode release is shown in table 3.3.5. the warm-up time of built-in flashrom is shown in t able 3.3.6. note: although this product is a maskrom product, in order to consider as the same operation as a flashrom product, built-in flashrom warm-up time enters. figure 3.3.8 illustrates the timing for clearance of the stop mode halt state by an int errupt. figure 3.3.8 timing chart for stop mo de halt state cleared by interrupt table 3.3.5 example of warm-up time after releasing stop mode at f osch = 10 mhz, fs = 32.768 khz syscr2 syscr1 01 (2 8 ) 10 (2 14 ) 11 (2 16 ) 0 (fc) 25.6 s 1.638 ms 6.554 ms 1 (fs) 7.8 ms 500 ms 2000 ms table 3.3.6 example of warm-up time after built-i n flashrom (at the time of stop mode release) at f osch = 10 mhz, fs = 32.768 khz 0 (fc) 409.6 s (2 12 /f osch ) 1 (fs) 125 ms (2 12 /fs ) data data stop mode x1 a0 to a23 d0 to d15 rd wr interrupt for release halt warm-up time of internal osillator + warm-up time of built-in flashrom
tmp92cy23/cd23a 2009-08-28 92cy23-37 table 3.3.7 input buffer state table input buffer state in halt mode (stop) when the cpu is operating in halt mode (idle1/2) drve = ?1? drve = ?0? port name input function name during reset when used as function pin when used as input pin when used as function pin when used as input pin when used as function pin when used as input pin when used as function pin when used as input pin p00-p07 d0-d7 p10-p17 d8-d15 on upon external read (*1) p40-p47 ? p50-p57 ? p60-p67 ? p70(*2) ? off p71-p73 (*2) ? off off off off p74 int0 on on on on oscillator on off on p76 xt1 port off off off off p77 ? off ? ? ? ? p83 wait off off pc0 ta0in off pc1 int1 pc2 int2 pc3 int3 pd0 int4 int5 on pd1 tb1in0 off int6 on pd2 tb1in1 off int7 on pd3 rxd2 pd4 sclk2, 2cts on on pf0 ? off off pf1 rxd0 pf2 sclk0, 0cts on on pf3 ? off off pf4 rxd1, hssi( *4) pf5 sclk1, 1cts on on on an0-an7(*3) off off on off pg0-pg7 ki0-ki7 on on on on pl0-pl2 an8-an10(*3) an11(*3) off off off pl3 adtrg off pn0 sck0 pn1 sda0 pn2 si0, scl0 pn3 sck1 pn4 sda1 pn5 si1, scl1 on off off off off nmi ? am0,am1 ? on on x1 ? off off reset ? on on ? on ? on ? on ? *1: on upon external read. on: the buffer is always turned on. a current flows through the input buffer if the input pin is not driven. *2: port having a pull-up/pull-down resistor. off: the buffer is always turned off. *3: ain input does not cause a current to flow through the buffer. ? : not applicable *4: hssi input function is not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-38 table 3.3.8 output buffer state table output buffer state in halt mode (stop) when the cpu is operating in halt mode (idle1/2) drve = ?1? drve = ?0? port name output function name during reset when used as function pin when used as output pin when used as function pin when used as output pin when used as function pin when used as output pin when used as function pin when used as output pin p00-p07 d0-d7 p10-p17 d8-d15 off on upon external write (*1) off off p40-p47 a0-da7 p50-p57 a8-a15 p60-p67 a16-a23 p70(*2) rd on p71(*2) srwr p72(*2) srllb p73(*2) srlub off on on on on on on off p76 ? ? on(*3) ? on(*3) ? on(*3) ? oscillator on off on off off p77 xt2 port off on(*3) off on(*3) off on(*3) p80 0cs , ta1out p81 1cs , ta3out p82 2cs p83 3cs , ta5out on pd0 tb0out0 pd2 txd2 pd3 tb1out0 pd4 tb1out1, sclk2 pf0 txd0 off on on off pf1 ? ? ? ? ? pf2 sclk0, clk pf3 txd1, hsso( *4) on on on off pf4 ? ? ? ? ? pf5 sclk1, hsclk( *4) pn0 sck0 pn1(*3) so0, sda0 pn2(*3) scl0 pn3 sck1 pn4(*3) so1, sda1 pn5(*3) scl1 off on on on on off x2 ? on on ? on ? off ? off ? *1: on upon external write. on: the buffer is always turned on. when the bus is released, however, output buffers for some pins are turned off. *2: port having a pull-up resistor (programmable) off: the buffer is always turned off. *3: open-drain output pin. ? : not applicable *4: hsso and hsclk output functions are not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-39 3.4 interrupts interrupts are controlled by the cpu interrupt mask register and by the built-in interrupt controller. the tmp92cy23 has a total of 50 interrupts, tmp92cd23a has a total of 51 interrupts. interrupts generated by cpu: 9 sources software interrupts: 8 sources illegal instruction interrupt: 1 source internal interrupts: tmp92cy23: 32 sources, tmp92cd2 3a: 33 sources internal i/o interrupts: tmp92cy23: 24 sources, tmp92cd23a: 25 sources micro dma transfer end interrupts: 8 sources external interrupts: 9 sources interrupts on external pins (int0 to int7, nmi ) a fixed individual interrupt vector number is assigned to each interrupt source. any one of six levels of priority can also be assigned to each maskable interrupt. non-maskable interrupts have a fixed priority level of 7, the highest level. when an interrupt is generated, the interrupt controller sends the priority of that interrupt to the cpu. when more than one interrupt is generated simultaneously, the interrupt controller sends the priority value of the interrupt with the highest priority to the cpu. (the highest priority level is 7, the level used for non-maskable interrupts.) the cpu compares the interrupt priority level which it receives with the value held in the cpu interrupt mask register . if the prio rity level of the interrupt is greater than or equal to the value in the interrupt mask register, the cpu accepts the interrupt. however, software interrupts and illegal instruction interrupts generated by the cpu are processed irrespective of the value in . the value in the interrupt mask register can be changed using the ei instruction (ei num sets to num). for example, the command ei 3 enables the acceptance of all non-maskable interrupts and of maskable interrupts whose priority level, as set in the interrupt controller, is 3 or higher. the commands ei and ei 0 enable the acceptance of all non-maskable interrupts and of maskable interrupt s with a priority level of 1 or above (hence both are equivalent to the command ei 1). the di instruction (sets to 7) is exactly equivalent to the ei 7 instruction. the di instruction is used to disable all maskable interrupts (since the priority level for maskable interrupts ranges from 1 to 6). the ei instruction takes effect as soon as it is executed. in addition to the general purpose interrupt pr ocessing mode described above, there is also a micro dma processing mode. in micro dma mode the cpu automatically transfers data in one-byte, two-byte or four-byte blocks; this mode allows high-speed data transf er to and from internal and external memory and internal i/o ports. in addition, the tmp92cy23/cd23a also has a software start function in which micro dma processing is requested in software rather than by an interrupt. figure 3.4.1 is a flowchart showing overall interrupt processing.
tmp92cy23/cd23a 2009-08-28 92cy23-40 figure 3.4.1 interrupt and mi cro dma processing sequence micro dma soft start request interrupt processing interrupt vector calue ?v? read interrupt request f/f clear interrupt specified by micro dma start vector ? push pc push sr sr level of accepted interrupt + 1 intnest intnest + 1 pc (ffff00h + v) interrupt processing program reti instruction pop sr pop pc intnest intnest ? 1 end clear interrupt request flag yes no data transfer by micro dma count count ? 1 count = 0 no clear vector register generating micro dma transfer end interrupt inttc yes micro dma processing general-purpose interrupt processing
tmp92cy23/cd23a 2009-08-28 92cy23-41 3.4.1 general-purpose interrupt processing when the cpu accepts an interrupt, it usually performs the following sequence of operations. however, in the case of software interrupts and illegal instruction interrupts generated by the cpu, the cpu sk ips steps (1) and (3), and executes only steps (2), (4) and (5). (1) the cpu reads the interrupt vector from the interrupt controller. when more than one interrupt with the same priority level has been generated simultaneously, the interrupt controller gene rates an interrupt vector in accordance with the default priority and clears the interrupt requests. (the default priority is determined as follows: the smaller the vector value, the higher the priority.) (2) the cpu pushes the program counter (pc) and status register (sr) onto the top of the stack (pointed to by xsp). (3) the cpu sets the value of the cpu?s interrupt mask register to the priority level for the accepted interrupt plus 1. howe ver, if the priority level for the accepted interrupt is 7, the register?s value is set to 7. (4) the cpu increments the interrupt nesting counter intnest by 1. (5) the cpu jumps to the address given by adding the contents of address ffff00h + the interrupt vector, then starts the interrupt processing routine. on completion of interrupt processing, the ret i instruction is used to return control to the main routine. reti restores the contents of the program counter and the status register from the stack and decrements the interrupt nesting counter intnest by 1. non-maskable interrupts cannot be disabled by a user program. maskable interrupts, however, can be enabled or disabled by a user program. a program can set the priority level for each interrupt source. (a priority level setting of 0 or 7 will disable an interrupt request.) if an interrupt request is received for an inte rrupt with a priority level equal to or greater than the value set in the cpu interrupt mask register , the cpu will accept the interrupt. the cpu interrupt mask register is then set to the value of the priority level for the accepted interrupt plus 1. if during interrupt processing, an interrupt is generated with a higher priority than the interrupt currently being processed, or if, during the processing of a non-maskable interrupt processing, a non-maskable interrupt request is generated from another source, the cpu will suspend the routine which it is currently executing and accept the new interrupt. when processing of the new interrupt has been completed, the cpu will resume processing of the suspended interrupt. if the cpu receives another interrupt request while performing processing steps (1) to (5), the new interrupt will be sampled immediately af ter execution of the first instruction of its interrupt processing routine. specifying di as the start instruction disables nesting of maskable interrupts. a reset initializes the interrupt mask register to ?111?, disabling all maskable interrupts. table 3.4.1 shows the tmp92cy23/cd23a interrupt vectors and micro dma start vectors. ffff00h to ffffffh (256 bytes) is de signated as the interrupt vector area.
tmp92cy23/cd23a 2009-08-28 92cy23-42 table 3.4.1 tmp92cy23/cd23a interrupt vectors and micro dma start vectors default priority type interrupt source and source of micro dma request vector value address refer to vector micro dma start vector 1 reset or [swi0] instruction 0000h ffff00h 2 [swi1] instruction 0004h ffff04h 3 illegal instruction or [swi2] instruction 0008h ffff08h 4 [swi3] instruction 000ch ffff0ch 5 [swi4] instruction 0010h ffff10h 6 [swi5] instruction 0014h ffff14h 7 [swi6] instruction 0018h ffff18h 8 [swi7] instruction 001ch ffff1ch 9 nmi : external interrupt input pin 0020h ffff20h 10 non- maskable intwd: watchdog timer 0024h ffff24h ? micro dma ? ? ? (note1) 11 int0: int0 pin input 0028h ffff28h 0ah ( note 2) 12 int1: int1 pin input 002ch ffff2ch 0bh ( note 2) 13 int2: int2 pin input 0030h ffff30h 0ch ( note 2) 14 int3: int3 pin input 0034h ffff34h 0dh ( note 2) 15 int4: int4 pin input 0038h ffff38h 0eh ( note 2) 16 int5: int5 pin input 003ch ffff3ch 0fh ( note 2) 17 int6: int6 pin input 0040h ffff40h 10h ( note 2) 18 int7: int7 pin input 0044h ffff44h 11h ( note 2) 19 intta0: 8-bit timer 0 0048h ffff48h 12h 20 intta1: 8-bit timer 1 004ch ffff4ch 13h 21 intta2: 8-bit timer 2 0050h ffff50h 14h 22 intta3: 8-bit timer 3 0054h ffff54h 15h 23 intta4: 8-bit timer 4 0058h ffff58h 16h 24 intta5: 8-bit timer 5 005ch ffff5ch 17h 25 (reserved) 0060h ffff60h 18h 26 (reserved) 0064h ffff64h 19h 27 intrx0: serial receive (channel 0) 0068h ffff68h 1ah ( note 2) 28 inttx0: serial transmission (channel 0) 006ch ffff6ch 1bh 29 intrx1: serial receive (channel 1) 0070h ffff70h 1ch ( note 2) 30 inttx1: serial transmission (channel 1) inthsc: high speed serial (note4) 0074h ffff74h 1dh 31 intrx2: serial receive (channel 2) 0078h ffff78h 1eh ( note 2) 32 inttx2: serial transmission (channel 2) 007ch ffff7ch 1fh 33 (reserved) 0080h ffff80h 20h 34 (reserved) 0084h ffff84h 21h 35 intnsbe0: sbi0 i2cbus transfer end 0088h ffff88h 22h 36 (reserved) 008ch ffff8ch 23h 37 intnsbe1: sbi1 i2cbus transfer end 0090h ffff90h 24h 38 (reserved) 0094h ffff94h 25h 39 (reserved) 0098h ffff98h 26h 40 (reserved) 009ch ffff9ch 27h 41 (reserved) 00a0h ffffa0h 28h 42 (reserved) 00a4h ffffa4h 29h 43 inttb00: 16-bit timer 0 00a8h ffffa8h 2ah 44 inttb01: 16-bit timer 0 00ach ffffach 2bh 45 inttbo0: 16-bit timer 0 (overflow) 00b0h ffffb0h 2ch 46 inttb10: 16-bit timer 1 00b4h ffffb4h 2dh 47 inttb11: 16-bit timer 1 00b8h ffffb8h 2eh 48 inttbo1: 16-bit timer 1 (overflow) 00bch ffffbch 2fh 49 maskable intad: ad conversion end 00c0h ffffc0h 30h
tmp92cy23/cd23a 2009-08-28 92cy23-43 default priority type interrupt source and source of micro dma request vector value address refer to vector micro dma start vector 50 intp0: protect 0 (write to sfr) 00c4h ffffc4h 31h 51 intrtc: special timer for clock 00c8h ffffc8h 32h 52 (reserved) 00cch ffffcch 33h 53 inttc0: micro dma end (channel 0) 00d0h ffffd0h 34h 54 inttc1: micro dma end (channel 1) 00d4h ffffd4h 35h 55 inttc2: micro dma end (channel 2) 00d8h ffffd8h 36h 56 inttc3: micro dma end (channel 3) 00dch ffffdch 37h 57 inttc4: micro dma end (channel 4) 00e0h ffffe0h 38h 58 inttc5: micro dma end (channel 5) 00e4h ffffe4h 39h 59 inttc6: micro dma end (channel 6) 00e8h ffffe8h 3ah 60 inttc7: micro dma end (channel 7) 00ech ffffech 3bh ? to ? maskable (reserved) 00f0h : 00fch fffff0h : fffffch ? to ? note 1: when initiating micro dma, set at edge detect mode. note 2: micro dma default priority. micro dma initiation takes priority over other maskable interrupts. note 3: specify the hscsel register when selecting inttx1 or inthsc that have the same interrupt factor in the default priority 30. note4: the inthsc interrupt is not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-44 3.4.2 micro dma processing in addition to general purpose interrupt processing, the tmp92cy23/cd23a also includes a micro dma function. micro dma proc essing for interrupt requests set by micro dma is performed at the highest priority leve l for maskable interrupts (level 6), regardless of the priority level of the interrupt source. because the micro dma function is implemented through the cpu, when the cpu is placed in a stand-by state by a halt instruct ion, the requirements of the micro dma will be ignored (pending). micro dma supports 8 channels and can be tr ansferred continuously by specifying the micro dma burst function as below. (1) micro dma operation when an interrupt request is generated by an interrupt source specified by the micro dma start vector register, the micro dma triggers a micro dma request to the cpu at interrupt priority level 6 and starts processing the request. the eight micro dma channels allow micro dma processing to be set for up to eight types of interrupt at once. when micro dma is accepted, the interrupt request flip-flop assigned to that channel is cleared. data in one-byte, two-byte or four-byte blocks, is automatically transferred at once from the transfer source address to the transfer destination address set in the control register, and the tr ansfer counter is decremented by 1. if the value of the counter after it has been decremented is not 0, dma processing ends with no change in the value of the micro dma start vector register. if the value of the decremented counter is 0, a micro dma transfer end interrupt (inttc0 to inttc7) is sent from the cpu to the interrupt controll er. in addition, the micro dma start vector register is cleared to ?0?, the next micro dma operation is disabled and micro dma processing terminates. if micro dma requests are set simultaneously for more than one channel, priority is not based on the interrupt priority level but on the channel number: the lower the channel number, the higher the priority (channel 0 thus has the highest priority and channel 7 the lowest). if an interrupt request is triggered for the interrupt source in use during the interval between the time at which the micro dma star t vector is cleared and the next setting, general purpose interrupt processing is performed at the interrupt level set. therefore, if the interrupt is only being used to initiate micro dma (and not as a general-purpose interrupt), the interrupt level should first be set to 0 (i.e., interrupt requests should be disabled). if using micro dma and general-purpose inte rrupts together, first set the level of the interrupt used to start micro dma processing lower than all the other interrupt levels. (note) in this case, the cause of general interrupt is limited to the edge interrupt. the priority of the micro dma transfer end interrupt (inttc0 to inttc3) is defined by the interrupt level and the default prio rity as the same as the other maskable interrupt. note: if the priority level of micro dma is set higher than that of other interrupts, cpu operates as follows. in case intxxx interrupt is generated first and then intyyy interrupt is generated between checking ?interrupt specified by micro dma start vector? (in the figure 3.4.1) and reading interrupt vector with setting below. th e vector shifts to that of intyyy at the time. this is because the priority level of intyyy is higher than that of intxxx. in the interrupt routine, cpu reads the vector of intyyy because cheking of micro dma has finished. and intyyy is generated regardless of transfer counter of micro dma. intxxx: level 1 without micro dma intyyy: level 6 with micro dma
tmp92cy23/cd23a 2009-08-28 92cy23-45 if micro dma and general purpose interrupt s are being used together as described above, the level of the interrupt which is being used to initiate micro dma processing should first be set to a lower value than all the other interrupt levels. in this case, edge triggered interrupts are the only kinds of general interrupts which can be accepted. although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. accordingl y, micro dma can only access 16 mbytes. three micro dma transfer modes are supported: one-byte transfers, two-byte transfer and four-byte transfer. after a transfer in any mode, the transfer source and transfer destination addresses will either be incremented or decremented, or will remain unchanged. this simplifies the transfer of data from memory to memory, from i/o to memory, from memory to i/o, and fr om i/o to i/o. for details of the various transfer modes, see section 3.4. 2 (4), detailed description of the transfer mode register. since a transfer counter is a 16-bit counter, up to 65536 micro dma processing operations can be performed per interrupt source (provided that the transfer counter for the source is initially set to 0000h). micro dma processing can be initiated by any one of 40 different interrupts ? the 39 interrupts shown in the micro dma start vectors in table 3.4.1 and a micro dma soft start. figure 3.4.2 shows a 2-byte transfer carried out us ing a mi cro dma cycle in transfer destination address inc mode (micro dma transfers are the same in every mode except counter mode). (the conditions for this cycle are as follows: this cycle is based on an external 8-bit bus, 0 waits, sou rce/transfer destination addresses both even-numbered values.) figure 3.4.2 timing for micro dma cycle state (1), (2): instruction fetch cycle (prefetc hes the next instruction code) if the instruction queue buffer is full, this cycle becomes a dummy cycle. state (3): micro dma read cycle state (4): micro dma write cycle state (5): (the same as in state (1), (2)) src 1 state f sys a 0 to a23 (1) dst (2) (3) (4) (5)
tmp92cy23/cd23a 2009-08-28 92cy23-46 (2) soft start function the tmp92cy23/cd23a can initiate micro dma either with an interrupt or by using the micro dma soft start function, in which micro dma is initiated by a write cycle which writes to the register dmar. writing ?1? to any bit of the register dmar causes micro dma to be performed once (if write ?0? to each bit, micro dma doesn?t operate). on completion of the transfer, the bits of dmar which support the end channel are automatically cleared to ?0?. only one channel can be set for dma request at once. (do not write ?1? to plural bits) when writing again ?1? to the dmar register, check whether the bit is 0 before writing 1. if read ?1?, micro dma transfer isn?t started yet. when a burst is specified by the register dmab, data is transferred continuously from the initiation of micro dma until the value in the micro dma transfer counter is ?0? after start up of the micro dma. if exec ute soft start during micro dma transfer by interrupt source, micro dma transfer counter doesn?t change. don?t use read-modify-write instruction to avoid writing to other bits by mistake. symbol name address 7 6 5 4 3 2 1 0 dreq7 dreq6 dreq5 dreq4 dre q3 dreq2 dreq1 dreq0 r/w 0 0 0 0 0 0 0 0 dmar dma request 109h (prohibit rmw) 1: dma request in software (3) transfer control registers the transfer source address and the tran sfer destination address are set in the following registers. an instruction of the form ldc cr, r can be used to set these registers. channel 0 dmas0 dma source address register 0: only use lsb 24 bits. dmad0 dma destination address register 0: only use lsb 24 bits. dmac0 dma counter register 0: 1 to 65536. dmam0 dma mode register 0. channel 7 dmas7 dma source address register 7. dmad7 dma destination address register 7. dmac7 dma counter register 7. dmam7 dma mode register 7. 8 bits 16 bits 32 bits
tmp92cy23/cd23a 2009-08-28 92cy23-47 (4) detailed description of the transfer mode register 0 0 0 mode dmam0 to dmam7 dmamn[4:0] mode description execution state number 0 0 0 z z destination inc mode (dmadn + ) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states 0 0 1 z z destination dec mode (dmadn ? ) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states 0 1 0 z z source inc mode (dmadn) (dmasn + ) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states 0 1 1 z z source dec mode (dmadn) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states 1 0 0 z z source and destination inc mode (dmadn + ) (dmasn + ) dmacn dmacn ? 1 if dmacn = 0 then inttcn 6 states 1 0 1 z z source and destination dec mode (dmadn ? ) (dmasn ? ) dmacn dmacn ? 1 if dmacn = 0 then inttcn 6 states 1 1 0 z z source and destination fixed mode (dmadn) (dmasn) dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states 1 1 1 0 0 counter mode dmasn dmasn + 1 dmacn dmacn ? 1 if dmacn = 0 then inttcn 5 states zz: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = (reserved) note1: the execution state number shows number of best case (1-state memory access). 1state = 50ns at f sys = 20mhz note2: n stands for the micro dma channel number (0 to 7) dmadn + /dmasn + : post-increment (register value is incremented after transfer) dmadn ? /dmasn ? : post-decrement (register value is decremented after transfer) ?i/o? signifies fixed memory addresses; ?memory? signifies incremented or decremented memory addresses. note3: the transfer mode register should not be set to any value other than those listed above.
tmp92cy23/cd23a 2009-08-28 92cy23-48 3.4.3 interrupt controller operation the block diagram in figure 3.4.3 shows the interrupt circuits. the left hand side of the diagram shows the interrupt contr oller circu it. the right hand side shows the cpu interrupt request signal circuit and the halt release circuit. for each of the 50 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priori ty setting register and a micro dma start vector register. the interrupt request flag latches interrupt requests from the peripherals. the flag is cleared to ?0? in the following cases: when a reset occurs, when the cpu reads the channel vector of an interrupt it has received, when the cpu receives a mi cro dma request (when micro dma is set), when a micro dma burst transfer is terminated, and when an instruction that clears the interrupt for that channel is executed (by writing a micro dma start vector to the intclr register). an interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting re gister (e.g., intepad or inte01). 6 interrupt priorities levels (1 to 6) are provided. setting an interrupt source?s priority level to 0 (or 7) disables interrupt requests from that sou rce. the priority of no n-maskable interrupt (watchdog timer interrupts) is fixed at 7. if more than one interrupt request with a given priority level are generated simultaneously, the default priority (the inte rrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. the 3rd and 7th bit of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. if several interrupts are gene rated simultaneously, the interrupt controller sends the interrupt request for the interrupt with the highest priority and the interrupt?s vector address to the cpu. the cpu compares the mask value set in of the status register (sr) with the priority level of the re quested interrupt; if the latter is higher, the interrupt is accepted. then the cpu sets sr to the priority level of the accepted interrupt + 1. hence, during processing of the accepted interrupt, new interrupt requests with a priority value equal to or higher than the value set in sr (e.g., interrupts with a priority higher than the interrupt being processed) will be accepted. when interrupt processing has been co mpleted (e.g., after execution of a reti instruction), the cpu restores to sr the priority value which was saved on the stack before the interrupt was generated. the interrupt controller also includes eight registers which are used to store the micro dma start vector. writing the start vector of the interrupt source for the micro dma processing (see table 3.4.1), enables the corresponding interrupts to be processed by micro dm a pr ocessing. the values must be set in the micro dma parameter registers (e.g., dmas and dmad) prior to micro dma processing.
tmp92cy23/cd23a 2009-08-28 92cy23-49 figure 3.4.3 block diagram of interrupt controller int01 to int4, intrtc, input key interrupt re q uest si g nal if iff = 7 then 0 micro dma start vector setting registe r inttc0 inttc1 inttc2 inttc3 inttc4 inttc5 inttc6 inttc7 v = d0h v = d4h v = d8h v = dch v = e0h v = e4h v = e8h v = ech soft start micro dm a counter 0 interrupt 6 inttc0 during idle1 45 3 3 3 1 6 1 7 3 3 8 6 51 8 input or micro dma channel priority decoder priority encoder dma0v dma1v : dma7v reset interrupt request f/f reset decode r reset priority setting register v = 20h v = 24h interrupt controller cpu s q r v = 28h v = 2ch v = 30h v = 34h v = 38h v = 3ch v = 40h v = 44h v = 48h v = 4ch d q clr y1 y2 y3 y4 y5 y6 a b c dn dn + 1 dn + 2 interrupt request f/f interrupt vector read micro dma acknowledge interrupt request f/f dn + 3 a b c i n t errup t vector read d2 d3 d4 d5 d6 d7 selector s q r 0 1 2 3 4 5 6 7 a b c d0 d1 interrupt vector read interrupt mask f/f micro dma request halt release if intrq2 to 0 iff 2 to 0 then 1. intrq2 to 0 iff2 to 0 interrupt level detect reset ei 1 to 7 di interrupt request signal during stop micro dma channel specification reset intwd int0 int1 int2 int3 int4 int5 int6 int7 intta0 intta1 s interrupt vector generator highest priority interrupt level select 1 2 3 4 5 6 7 d5 d4 d3 d2 d1 d0 d q clr nmi
tmp92cy23/cd23a 2009-08-28 92cy23-50 (1) interrupt level se tting registers symbol name address 7 6 5 4 3 2 1 0 int1 int0 i1c i1m2 i1m1 i1m0 i0c i0m2 i0m1 i0m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte01 int0 & int1 enable 00d0h 1:int1 interrupt request level 1:int0 interrupt request level int3 int2 i3c i3m2 i3m1 i3m0 i2c i2m2 i2m1 i2m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte23 int2& int3 enable 00d1h 1:int3 interrupt request level 1:int2 interrupt request level int5 int4 i5c i5m2 i5m1 i5m0 i4c i4m2 i4m1 i4m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte45 int4& int5 enable 00d2h 1:int5 interrupt request level 1:int4 interrupt request level int7 int6 i7c i7m2 i7m1 i7m0 i6c i6m2 i6m1 i6m0 r r/w r r/w 0 0 0 0 0 0 0 0 inte67 int6& int7 enable 00d3h 1:int7 interrupt request level 1:int6 interrupt request level intta1(tmra1) intta0(tmra0) ita1c ita1m2 ita1m1 ita1m0 it a0c ita0m2 ita0m1 ita0m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta01 intta0 & intta1 enable 00d4h 1: intta1 interrupt request level 1:intta0 interrupt request level intta3(tmra3) intta2(tmra2) ita3c ita3m2 ita3m1 ita3m0 it a2c ita2m2 ita2m1 ita2m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta23 intta2 & intta3 enable 00d5h 1: intta3 interrupt request level 1:intta2 interrupt request level intta5(tmra5) intta4(tmra4) ita5c ita5m2 ita5m1 ita5m0 it a4c ita4m2 ita4m1 ita4m0 r r/w r r/w 0 0 0 0 0 0 0 0 inteta45 intta4 & intta5 enable 00d6h 1: intta5 interrupt request level 1: intta4 interrupt request level lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests interrupt request flag
tmp92cy23/cd23a 2009-08-28 92cy23-51 symbol name address 7 6 5 4 3 2 1 0 inttx0 intrx0 itx0c itx0m2 itx0m1 itx0m0 irx0c irx0m2 irx0m1 irx0m0 r r/w r r/w 0 0 0 0 0 0 0 0 intes0 intrx0 & inttx0 enable 00d8h 1:inttx0 interrupt request level 1:intrx0 interrupt request level inttx1/inthsc (note) intrx1 itx1c itx1m2 itx1m1 itx1m0 irx1c irx1m2 irx1m1 irx1m0 r r/w r r/w 0 0 0 0 0 0 0 0 intes1hsc intrx1 & inttx1/ inthsc enable 00d9h 1:inttx1 interrupt request level 1:intrx1 interrupt request level inttx2 intrx2 itx2c itx2m2 itx2m1 itx2m0 irx2c irx2m2 irx2m1 irx2m0 r r/w r r/w 0 0 0 0 0 0 0 0 intes2 intrx2 & inttx2 enable 00dah 1:inttx2 interrupt request level 1:intrx2 interrupt request level ? intsbe0 ? ? ? ? isbe0c isbe0m2 isbe0m1 isbe0m0 ? ? r r/w ? ? ? ? 0 0 0 0 intesb0 intsbe0 enable 00dch always write ?0? 1:intsbe0 interrupt request level ? intsbe1 ? ? ? ? isbe1c isbe1m2 isbe1m1 isbe1m0 ? ? r r/w ? ? ? ? 0 0 0 0 intesb1 intsbe1 enable 00ddh always write ?0? 1:intsbe1 interrupt request level inttb01(tmrb0) inttb00(tmrb0) itb01c itb01m2 itb01m1 itb01m0 i tb00c itb00m2 itb00m1 itb00m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetb0 inttb00 & inttb01 enable 00e0h 1:inttb01 interrupt request level 1:inttb00 interrupt request level ? inttbo0(tmrb0) ? ? ? ? itbo0c itbo0m2 itbo0m1 itbo0m0 ? ? r r/w ? ? ? ? 0 0 0 0 intetbo0 inttbo0 (overflow) enable 00e1h always write ?0? 1:inttbo0 interrupt request level inttb11(tmrb1) inttb10(tmrb1) itb11c itb11m2 itb11m1 itb11m0 i tb10c itb10m2 itb10m1 itb10m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetb1 inttb10 & inttb11 enable 00e2h 1:inttb11 interrupt request level 1:inttb10 interrupt request level note: inthsc interrupt is not built into tmp92cy23. lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests interrupt request flag
tmp92cy23/cd23a 2009-08-28 92cy23-52 symbol name address 7 6 5 4 3 2 1 0 ? inttbo1(tmrb1) ? ? ? ? itbo1c itbo1m2 itbo1m1 itbo1m0 ? ? r r/w ? ? ? ? 0 0 0 0 intetbo1 inttbo1 (overflow) enable 00e3h always write 0 1:inttbo1 interrupt request level intp0 intad ip0c ip0m2 ip0m1 ip0m0 iadc iadm2 iadm1 iadm0 r r/w r r/w 0 0 0 0 0 0 0 0 intepad intp0 & intad enable 00e4h 1:intp0 interrupt request level 1:intad interrupt request level ? intrtc ? ? ? ? irc irm2 irm1 irm0 ? ? r r/w ? ? ? ? 0 0 0 0 intertc intrtc enable 00e5h always write ?0? 1:intrtc interrupt request level nmi intwdt incnm ? ? ? incwd ? ? ? r ? r ? 0 ? ? ? 0 ? ? ? intnmwdt nmi & intwdt enable 00efh 1: nmi always write ?0? 1:intwdt always write 0 inttc1(dma1) inttc0(dma0) itc1c itc1m2 itc1m1 itc1m0 itc0c itc0m2 itc0m1 itc0m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetc01 inttc0 & inttc1 enable 00f0h 1:inttc1 interrupt request level 1:inttc0 interrupt request level inttc3(dma3) inttc2(dma2) itc3c itc3m2 itc3m1 itc3m0 itc2c itc2m2 itc2m1 itc2m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetc23 inttc2 & inttc3 enable 00f1h 1:inttc3 interrupt request level 1:inttc2 interrupt request level inttc5(dma5) inttc4(dma4) itc5c itc5m2 itc5m1 itc5m0 itc4c itc4m2 itc4m1 itc4m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetc45 inttc4 & inttc5 enable 00f2h 1:inttc5 interrupt request level 1:inttc4 interrupt request level inttc7(dma7) inttc6(dma6) itc7c itc7m2 itc7m1 itc7m0 itc6c itc6m2 itc6m1 itc6m0 r r/w r r/w 0 0 0 0 0 0 0 0 intetc67 inttc6 & inttc7 enable 00f3h 1:inttc7 interrupt request level 1:inttc6 interrupt request level lxxm2 lxxm1 lxxm0 function (write) 0 0 0 disables interrupt requests 0 0 1 sets interrupt priority level to 1 0 1 0 sets interrupt priority level to 2 0 1 1 sets interrupt priority level to 3 1 0 0 sets interrupt priority level to 4 1 0 1 sets interrupt priority level to 5 1 1 0 sets interrupt priority level to 6 1 1 1 disables interrupt requests interrupt request flag
tmp92cy23/cd23a 2009-08-28 92cy23-53 (2) external interrupt control symbol name address 7 6 5 4 3 2 1 0 n m i r e e w 0 iimc interrupt input mode control 00f6h (prohibit rmw) nmi 0:falling 1:falling and rising i7le i6le i5le i4le i3le i2le i1le i0le w 0 0 0 0 0 0 0 0 iimc2 interrupt input mode control2 00fah (prohibit rmw) int7 0:edge 1:level int6 0:edge 1:level int5 0:edge 1:level int4 0:edge 1:level int3 0:edge 1:level int2 0:edge 1:level int1 0:edge 1:level int0 0:edge 1:level i7edge i6edge i5edge i4edge i3edge i2edge i1edge i0edge w 0 0 0 0 0 0 0 0 iimc3 interrupt input mode control3 00fbh (prohibit rmw) int7 0: rising /high 1: falling /low int6 0: rising /high 1: falling /low int5 0: rising /high 1: falling /low int4 0: rising /high 1: falling /low int3 0: rising /high 1: falling /low int2 0: rising /high 1: falling /low int1 0: rising /high 1: falling /low int0 0: rising /high 1: falling /low clrv7 clrv6 clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 0 0 intclr interrupt clear control 00f8h (prohibit rmw) clear the interrupt request flag by the writing of a micro dma starting vector note 1: disable int0 to int7 reques ts before changing int0 to int7 pins mode from level sense to edge sense. setting example for case of int0: di ld (iimc2) ,xxxxxx0-b ; change from ?level? to ?edge?. ld (intclr), 0ah ; clear interrupt request flag. nop ; wait ei execution. nop nop ei x: don?t care, ? : no change note 2: see electrical characteristics in sect ion 4 for external interrupt input pulse width. note 3: in a setup of a port, when choosing a 16-bit timer input and performing capture control, int5 and int6 operate not according to a setup of iimc2 and iimc3 register but according to a setup of tb1mod.
tmp92cy23/cd23a 2009-08-28 92cy23-54 table 3.4.2 settings of external interrupt pin function interrupt pin shared pin mode setting method rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int0 p74 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int1 pc1 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int2 pc2 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int3 pc3 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int4 pd0 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int5 pd1 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int6 pd2 low level iimc2 = ?1?, iimc3 = ?1? rising edge iimc2 = ?0?, iimc3 = ?0? falling edge iimc2 = ?0?, iimc3 = ?1? high level iimc2 = ?1?, iimc3 = ?0? int7 pd3 low level iimc2 = ?1?, iimc3 = ?1?
tmp92cy23/cd23a 2009-08-28 92cy23-55 (3) sio receive interrupt control symbol name address 7 6 5 4 3 2 1 0 ? ir2le ir1le ir0le w w 0 1 1 1 simc sio interrupt mode control f5h (prohibit rmw) always write ?1? (note) 0: intrx2 edge mode 1: intrx2 level mode 0: intrx1 edge mode 1: intrx1 level mode 0: intrx0 edge mode 1: intrx0 level mode note: when you use interruption, be sure to set ?1? as the bit 7 of a simc register. intrx2 level enable 0 edge detect intrx2 1 ?h? level intrx2 intrx1 level enable 0 edge detect intrx1 1 ?h? level intrx1 intrx0 rising edge enable 0 edge detect intrx0 1 ?h? level intrx0
tmp92cy23/cd23a 2009-08-28 92cy23-56 (4) interrupt request flag clear register the interrupt request flag is cleared by writing the appropriate micro dma start vector, as given in table 3.4.1, to the register intclr. fo r exam ple, to clear the interrupt flag int0, perform the following register operation after execution of the di instruction. intclr 0ah clears interrupt request flag int0. symbol name address 7 6 5 4 3 2 1 0 clrv7 clrv6 clrv5 clrv4 clrv3 clrv2 clrv1 clrv0 w 0 0 0 0 0 0 0 0 intclr interrupt clear control f8h (prohibit rmw) interrupt vector (5) micro dma start vector registers these registers assign micro dma processing to sets which source corresponds to dma. the interrupt source whose micro dma start vector value matches the vector set in one of these registers is designated as the micro dma start source. when the micro dma transfer counter value reaches ?0?, the micro dma transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro dma start vector register is cleared, and th e micro dma start source for the channel is cleared. therefore, in order for micro dma processing to continue, the micro dma start vector register must be set again during processing of the micro dma transfer end interrupt. if the same vector is set in the micro dma start vector registers of more than one channel, the lowest numbered channel takes priority. accordingly, if the same vector is set in the micro dma start vector registers for two different channels, the interrupt generated on the lower numbered channel is executed until micro dma transfer is complete. if th e micro dma start vector for this channel has not been set in the channel?s micro dm a start vector register again, micro dma transfer for the higher-numbered channel will be commenced. (this process is known as micro dma chaining.)
tmp92cy23/cd23a 2009-08-28 92cy23-57 symbol name address 7 6 5 4 3 2 1 0 dma0v5 dma0v4 dma0v3 dma0v2 dma0v1 dma0v0 r/w 0 0 0 0 0 0 dma0v dma0 start vector 100h dma0 start vector dma1v5 dma1v4 dma1v3 dma1v2 dma1v1 dma1v0 r/w 0 0 0 0 0 0 dma1v dma1 start vector 101h dma1 start vector dma2v5 dma2v4 dma2v3 dma2v2 dma2v1 dma2v0 r/w 0 0 0 0 0 0 dma2v dma2 start vector 102h dma2 start vector dma3v5 dma3v4 dma3v3 dma3v2 dma3v1 dma3v0 r/w 0 0 0 0 0 0 dma3v dma3 start vector 103h dma3 start vector dma4v5 dma4v4 dma4v3 dma4v2 dma4v1 dma4v0 r/w 0 0 0 0 0 0 dma4v dma4 start vector 104h dma4 start vector dma5v5 dma5v4 dma5v3 dma5v2 dma5v1 dma5v0 r/w 0 0 0 0 0 0 dma5v dma5 start vector 105h dma5 start vector dma6v5 dma6v4 dma6v3 dma6v2 dma6v1 dma6v0 r/w 0 0 0 0 0 0 dma6v dma6 start vector 106h dma6 start vector dma7v5 dma7v4 dma7v3 dma7v2 dma7v1 dma7v0 r/w 0 0 0 0 0 0 dma7v dma7 start vector 107h dma7 start vector
tmp92cy23/cd23a 2009-08-28 92cy23-58 (6) specification of a micro dma burst specifying the micro dma burst function ca uses micro dma transfer, once started, to continue until the value in the transfer counter register reaches ?0?. setting any of the bits in the register dmab which correspond to a micro dma channel (as shown below) to 1 specifies that any micro dma transfer on that channel will be a burst transfer. symbol name address 7 6 5 4 3 2 1 0 dbst7 dbst6 dbst5 dbst4 dbst3 dbst2 dbst1 dbst0 r/w 0 0 0 0 0 0 0 0 dmab dma burst 108h 1: dma burst request
tmp92cy23/cd23a 2009-08-28 92cy23-59 (7) notes the instruction execution unit and the bus interface unit in this cpu operate independently. therefore, immediately before an interrupt is generated, if the cpu fetches an instruction which clears the co rresponding interrupt request flag, the cpu may execute this instruction in between accepting the interrupt and reading the interrupt vector. in this case, the cpu will read the default vector 0004h and jump to interrupt vector address ffff04h. to avoid this, an instruction which clears an interrupt request flag should always be placed after a di instruction. and in the case of setting an interrupt enable again by ei instruction after the execution of clearing instruction, execute ei instruction after clearing and more than 3 ? instructions (e.g., ?nop? 3 times). if it placed ei instruction without waiting nop instruction after execution of clearing instruction, interrupt will be en abled before request flag is cleared. in the case of changing the value of the interrupt mask register by execution of pop sr instruction, disable an interrupt by di instruction before execution of pop sr instruction. in addition, please note that the following two circuits are exceptional and demand special attention. in level mode int0 is not an edge triggered interrupt. hence, in level mode the interrupt request flip-flop for int0 does not function. the peripheral interrupt request passes through the s input of the flip-flop and becomes the q output. if the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. int0 to int7 level mode if the cpu enters the interrupt response sequence as a result of int0 going from ?0? to ?1?, int0 must then be held at ?1? until the interrupt response sequence has been completed. if int0 to int7 are set to level mode so as to release a halt state, int0 must be held at ?1? from the time int0 changes from ?0? to ?1? until the halt state is released. (hence, it is necessary to ensure that input noise is not interpreted as a ?0?, causing int0 to revert to ?0? before the halt state has been released.) when the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. interrupt request flags must be cleared using the following sequence. di ld (iimc2), 00h ; switches from level to edge. ld (intclr), 0ah ; clears interrupt request flag. nop ; wait ei execution nop nop ei intrx0 to intrx2 in level mode (the register simc set to ?0?), the interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. it cannot be cleared by writing intclr register. note: the following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. int0 to int7: instructions which switch to level mode after an interrupt request has been generated in edge mode. the pin input changes from ?high to low? and ?low to high? after an interrupt request has been generated in level mode. (?h? ?l?, ?l? ?h?) intrx0 to intrx2: instructions which read the receive buffer.
tmp92cy23/cd23a 2009-08-28 92cy23-60 3.5 function of ports the tmp92cy23/cd23a i/o port pins are shown in table 3.5.1. in addition to functioning as general- purpose i/o ports, these pins are also used by the internal cpu and i/o functions. table 3.5.2 to table 3.5.4 list the i/o regist ers and thei r spec ifications. table 3.5.1 port functions (r: pu = with programmable pull-up resistor, u = with pull-up resistor) port name pin name number of pins i/o r i/o setting pin name for built-in function port 0 p00 to p07 8 i/o ? bit d0 to d7 port 1 p10 to p17 8 i/o ? bit d8 to d15 port 4 p40 to p47 8 i/o ? bit a0 to a7 port 5 p50 to p57 8 i/o ? bit a8 to a15 port 6 p60 to p67 8 i/o ? bit a16 to a23 p70 1 i/o pu bit rd p71 1 i/o pu bit srwr p72 1 i/o pu bit srllb p73 1 i/o pu bit srlub p74 1 input ? (fixed) int0 p76 1 i/o ? bit xt1 port 7 p77 1 i/o ? bit xt2 p80 1 output ? (fixed) 0cs , ta1out p81 1 output ? (fixed) 1cs , ta3out p82 1 output ? (fixed) 2cs port 8 p83 1 i/o ? bit 3cs , wait , ta5out pc0 1 input ? (fixed) ta0in pc1 1 input ? (fixed) int1 pc2 1 input ? (fixed) int2 port c pc3 1 input ? (fixed) int3 pd0 1 i/o ? bit int4,tb0out0 pd1 1 input ? (fixed) int5,tb1in0 pd2 1 i/o ? bit int6,tb1in1,txd2 pd3 1 i/o ? bit int7,tb1out0,rxd2 port d pd4 1 i/o ? bit tb1out1,sclk2, 2cts pf0 1 i/o ? bit txd0 pf1 1 i/o ? bit rxd0 pf2 1 i/o ? bit sclk0, 0cts , clk pf3 1 i/o ? bit txd1, hsso pf4 1 i/o ? bit rxd1, hssi port f pf5 1 i/o ? bit sclk1, 1cts , hsclk port g pg0 to pg7 8 input ? (fixed) an0 to an7,ki0 to ki7 port l pl0 to pl3 4 input ? (fixed) an8 to an11, adtrg (pl3) pn0 1 i/o ? bit sck0 pn1 1 i/o ? bit so0,sda0 pn2 1 i/o ? bit si0,scl0 pn3 1 i/o ? bit sck1 pn4 1 i/o ? bit so1,sda1 port n pn5 1 i/o ? bit si1,scl1 note: hsso,hssi and hsclk functions are not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-61 table 3.5.2 i/o registers and specifications (1/3) x: don?t care i/o register port pin name specification pn pncr pnfc pnfc2 pnode input port x 0 output port x 1 0 port 0 p00 to p07 d0 to d7 bus x x 1 none none input port x 0 output port x 1 0 port 1 p10 to p17 d8 to d15 bus x x 1 none none input port x 0 output port x 1 0 port 4 p40 to p47 a0 to a7 output x x 1 none none input port x 0 output port x 1 0 port 5 p50 to p57 a8 to a15 output x x 1 none none input port x 0 output port x 1 0 port 6 p60 to p67 a16 to a23 output x x 1 none none input port (without pull-up) 0 0 0 input port (with pull-up) 1 0 0 output port x 1 0 p70 rd output x x 1 input port (without pull-up) 0 0 0 input port (with pull-up) 1 0 0 output port x 1 0 p71 srwr x x 1 input port (without pull-up) 0 0 0 input port (with pull-up) 1 0 0 output port x 1 0 p72 srllb x x 1 input port (without pull-up) 0 0 0 input port (with pull-up) 1 0 0 output port x 1 0 p73 srlub x x 1 input port x 0 0 p74 int0 x 0 1 input port x 0 output port (?0? output ) 0 1 output port (?hz? output ) 1 1 p76 xt1 input x x none input port x 0 output port (?0? output ) 0 1 output port (?hz? output ) 1 1 port 7 p77 xt2 output x x none none none
tmp92cy23/cd23a 2009-08-28 92cy23-62 table 3.5.3 i/o registers and specifications (2/3) x: don?t care i/o register port pin name specification pn pncr pnfc pnfc2 pnode p80 to p81 output port x 0 0 0cs output x 1 0 p80 ta1out x x 1 1cs output x 1 0 p81 ta3out x x 1 output port x 0 p82 2 cs output x none 1 none input port x 0 0 0 output port x 1 0 0 wait input x 0 1 0 3cs output x 1 1 0 port 8 p83 ta5out x 1 0 1 none input port x 0 pc0 ta0in input x 1 input port x 0 pc1 int1 input x 1 input port x 0 pc2 int2 input x 1 input port x 0 port c pc3 int3 input x none 1 none none input port x 0 0 output port x 1 0 int4 input x 0 1 pd0 tb0out0 x 1 1 none input port x 0 0 int5input x 0 1 pd1 tb0in0 x none 1 0 input port x 0 0 0 output port x 1 0 0 int6 input x 0 0 1 tb0in1 input x 0 1 0 txd2 output (3-state) x 1 1 0 pd2 txd2 (open drain)output x 1 1 1 input port x 0 0 0 output port x 1 0 0 int7 input x 0 0 1 rxd2 input x 0 1 0 pd3 tb1out0 output x 1 1 0 input port x 0 0 0 output port x 1 0 0 sclk2 input , 2cts input x 0 0 1 sclk2 output x 1 0 1 port d pd4 tb1out1 x 1 1 0 none
tmp92cy23/cd23a 2009-08-28 92cy23-63 table 3.5.4 i/o registers and specifications (3/3) x: don?t care i/o register port pin name specification pn pncr pnfc pnfc2 siocnt pnode input port x 0 0 output port x 1 0 txd0 output (open drain output ) x 0 1 pf0 txd0 output (3-state) x 1 1 none input port x 0 0 output port x 1 0 pf1 rxd0 input x 0 1 none input port x 0 0 0 output port x 1 0 0 sclk0 input , 0cts input x 0 1 0 sclk0 output x 1 1 0 pf2 clk output x 1 0 1 none input port x 0 0 0 output port x 1 0 0 txd1 output (open drain output ) x 0 1 0 txd1 output (3-state) x 1 1 0 pf3 hsso output (3-state) (note) x 1 1 none 1 input port x 0 0 0 output port x 1 0 0 rxd1 input x 0 1 0 pf4 hssi input (note) x 0 1 none 1 input port x 0 0 0 output port x 1 0 0 sclk1 input , 1cts input x 0 1 0 sclk1 output x 1 1 0 port f pf5 hsclk output (note) x 1 1 none 1 none input port x 0 an0 to an7 input x 1 port g pg0 to pg7 ki0 to ki7 input x none x none none none input port x 0 pl0 to pl3 an8 to an11 input x 1 port l pl3 adtrg x none 0 none none none input port x 0 0 pn0 to pn5 output port x 1 0 sck0 input x 0 1 pn0 sck0 output x 1 1 so0 output x 0 1 pn1 sda0 input/output x 1 1 si0 input x 0 1 pn2 scl0 input/output x 1 1 sck1 input x 0 1 pn3 sck1 output x 1 1 so1 output x 0 1 pn4 sda1 input/output x 1 1 si1 input x 0 1 port n pn5 scl1 input/output x 1 1 none none none note: hsso,hssi and hsclk functions are not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-64 3.5.1 port 0 (p00 to p07) port 0 is an 8-bit general-purpose i/o port. bits can be individually set as either inputs or outputs by control register p0 cr and function register p0fc. in addition to functioning as a general-purpose i/o port, port 0 can also function as a data bus (d0 to d7). moreover, after reset release, since a device is set as an input port, when using it as a data bus (d0 to d7), it needs to set it as p0cr and p0fc. figure 3.5.1 port 1 interna data bus direction control (on bit basis) reset p0cr write r output latch p0 write s a selector b p0 read external access (data write) port 0 p00 to p07 (d0 to d7) function control p0fc write d0 to d7 external access (data read) output buffer
tmp92cy23/cd23a 2009-08-28 92cy23-65 port 0 register 7 6 5 4 3 2 1 0 bit symbol p07 p06 p05 p04 p03 p02 p01 p00 read/write r/w p0 (0000h) reset state data from external port (output latch register is cleared to ?0?) port 0 control register 7 6 5 4 3 2 1 0 bit symbol p07c p06c p05c p04c p03c p02c p01c p00c read/write w reset state 0 0 0 0 0 0 0 0 p0cr (0002h) function refer to following table port 0 function register 7 6 5 4 3 2 1 0 bit symbol p00f read/write w reset state 0 p0fc (0003h) function refer to following table port 0 function setting note1: a read-modify-write operation cannot be performed in p0cr and p0fc registers. note2: is bit x of p0cr register. figure 3.5.2 register for port 0 p0fc p0cr 0 1 0 input port 1 output port data bus (d0 to d7)
tmp92cy23/cd23a 2009-08-28 92cy23-66 3.5.2 port 1 (p10 to p17) port 1 is an 8-bit general-purpose i/o port. bits can be individually set as either inputs or outputs by control register p1 cr and function register p1fc. in addition to functioning as a general-purpose i/o port, port1 can also function as a data bus (d8 to d15). moreover, after reset release, since a device is set as an input port, when using it as a data bus (d8 to d15), it need s to set it as p1cr and p1fc. figure 3.5.3 port 1 internal data bus direction control (on bit basis) reset p1cr write r output latch p1 write s a selector b p1 read external access (data write) port 1 p10 to p17 (d8 to 15) function control p1fc write d8 to d15 external access (data read) output buffer
tmp92cy23/cd23a 2009-08-28 92cy23-67 port 1 register 7 6 5 4 3 2 1 0 bit symbol p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w p1 (0004h) reset state data from external port (output latch register is cleared to ?0?) port 1 control register 7 6 5 4 3 2 1 0 bit symbol p17c p16c p15c p14c p13c p12c p11c p10c read/write w reset state 0 0 0 0 0 0 0 0 p1cr (0006h) function refer to following table port 1 function register 7 6 5 4 3 2 1 0 bit symbol p10f read/write w reset state 0 p1fc (0007h) function refer to following table port 1 function setting note1: a read-modify-write operation cannot be performed in p1cr and p1fc registers. note2: is bit x of p1cr register. figure 3.5.4 register for port 1 p1fc p1cr 0 1 0 input port 1 output port data bus (d8 to d15)
tmp92cy23/cd23a 2009-08-28 92cy23-68 3.5.3 port 4 (p40 to p47) port4 is 8-bit general-purpose i/o ports. bits ca n be individually set as either inputs or outputs by control register p4cr and function register p4fc. in addition to functioning as a general-purpose i/o port, port4 can also function as an address bus (a0 to a7). moreover, after reset release, since a device is set as an input port, when using it as an address bus (a0 to a7), it need s to set it as p4cr and p4fc. figure 3.5.5 port 4 internal data bus direction control (on bit basis) reset p4cr write r output latch p4 write s b selector a p4 read port 4 p40 to p47 (a0 to a7) function control (on bit basis) p4fc write output buffer internal address bus a 0 to a7
tmp92cy23/cd23a 2009-08-28 92cy23-69 port 4 register 7 6 5 4 3 2 1 0 bit symbol p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w p4 (0010h) reset state data from external port (output latch register is cleared to ?0?) port 4 control register 7 6 5 4 3 2 1 0 bit symbol p47c p46c p45c p44c p43c p42c p41c p40c read/write w reset state 0 0 0 0 0 0 0 0 p4 (0012h) function 0: input 1: output port 4 function register 7 6 5 4 3 2 1 0 bit symbol p47f p46f p45f p44f p43f p42f p41f p40f read/write w reset state 0 0 0 0 0 0 0 0 p4fc (0013h) function 0: port 1: address bus (a0 to a7) note1: a read-modify-write operation cannot be performed in p4cr and p4fc registers. note2: when using as address bus a0 to a7, set p4fc after set p4cr. figure 3.5.6 register for port 4
tmp92cy23/cd23a 2009-08-28 92cy23-70 3.5.4 port 5 (p40 to p47) port5 is 8-bit general-purpose i/o ports. bits ca n be individually set as either inputs or outputs by control register p5cr and function register p5fc. in addition to functioning as a general-purpose i/o port, port 5 can also function as an address bus (a8 to a15). moreover, after reset release, since a device is set as an input port, when using it as an address bus (a8 to a15), it need s to set it as p5cr and p5fc. figure 3.5.7 port 5 internal data bus direction control (on bit basis) reset p5cr write r output latch p5 write s b selector a p5 read port 5 p50 to p57 (a8 to a15) function control (on bit basis) p5fc write output buffer internal address bus a 8 to a15
tmp92cy23/cd23a 2009-08-28 92cy23-71 port 5 register 7 6 5 4 3 2 1 0 bit symbol p57 p56 p55 p54 p53 p52 p51 p50 read/write r/w p5 (0014h) reset state data from external port (output latch register is cleared to ?0?) port 5 control register 7 6 5 4 3 2 1 0 bit symbol p57c p56c p55c p54c p53c p52c p51c p50c read/write w reset state 0 0 0 0 0 0 0 0 p5 (0016h) function 0: input 1: output port 5 function register 7 6 5 4 3 2 1 0 bit symbol p57f p56f p55f p54f p53f p52f p51f p50f read/write w reset state 0 0 0 0 0 0 0 0 p5fc (0017h) function 0: port 1: address bus (a8 to a15) note1: a read-modify-write operation cannot be performed in p5cr and p5fc registers. note2: when using as address bus a8 to a15, set p5fc after set p5cr. figure 3.5.8 register for port 5
tmp92cy23/cd23a 2009-08-28 92cy23-72 3.5.5 port 6 (p60 to p67) port 6 is an 8-bit general-purpose i/o port. bits can be individually set as either inputs or outputs by control register p6 cr and function register p6fc. in addition to functioning as a general-purpos e i/o port, port 6 can also function as an address bus (a16 to a23). moreover, after reset release, since a device is set as an input port, when using it as a address bus (a16 to a23), it need s to set it as p6cr and p6fc. figure 3.5.9 port 6 internal data bus direction control (on bit basis) reset p6cr write r output latch p6 write s b selector a p6 read port 6 p60 to p67 (a16 to a23) function control (on bit basis) p6fc write output buffer internal address bus a 16 to a23
tmp92cy23/cd23a 2009-08-28 92cy23-73 port 6 register 7 6 5 4 3 2 1 0 bit symbol p67 p66 p65 p64 p63 p62 p61 p60 read/write r/w p6 (0018h) reset state data from external port (output latch register is cleared to ?0?) port 6 control register 7 6 5 4 3 2 1 0 bit symbol p67c p66c p65c p64c p63c p62c p61c p60c read/write w reset state 0 0 0 0 0 0 0 0 p6cr (001ah) function 0: input 1: output port 6 function register 7 6 5 4 3 2 1 0 bit symbol p67f p66f p65f p64f p63f p62f p61f p60f read/write w reset state 0 0 0 0 0 0 0 0 p6fc (001bh) function 0: port 1: address bus (a16 to a23) note1: a read-modify-write operation cannot be performed in p6cr and p6fc registers. note2: when using as address bus a16 to a23, set p6fc after set p6cr. figure 3.5.10 register for port 6
tmp92cy23/cd23a 2009-08-28 92cy23-74 3.5.6 port 7 (p70 to p74, p76, p77) as for a port7, p70 to p73, and p76 and p77 are general-purpose i/o ports, and p74 is a port only for inputs. p76 and p77 become an open drain output, when it is set as an output port. moreover, p70 to p73 are ports with pull-up resistance. bits can be individually set as either inputs or outputs by control register p7 cr and function register p7fc. in addition to functioning as a general-pu rpose i/o port, port7 can also function as a cpu?s control. p70 to p73 has the function of rd strobe signal output as an object for external memory connection, and the output for sram control ( srwr , srllb and srlub ). p74 has the function of an external interrupt input (int0). p76 and p77 have the function of a low-frequency resonator connection (xt1, xt2). these setups become effective by setting ?1? as the applicable bit of p7cr and a p7fc register. the edge of the external interruption int0 and level selection are set up in iimc2 and iimc3 registers in an interruption controller. p70 to p74 become input mode by the reset action, and p76 and p77 become output mode (high impedance output). figure 3.5.11 port 7 (p70 to p73) internal data bus direction control ( on bit basis ) reset p7 read port p7 p70 ( rd ) p71 ( srwr ) p72 ( srllb ) p73 ( srlub ) p7 write output buffer s output latch p7cr write p7fc write function control (on bit basis) s a selector b rd , srwr srllb , srlub programmable pull-up p-ch s b selector a
tmp92cy23/cd23a 2009-08-28 92cy23-75 figure 3.5.12 port 7(p74) internal data bus function control (on bit basis) reset p7fc write p7 read select level/edge and select rising/falling iimc2 iimc3 int0 p74 (int0)
tmp92cy23/cd23a 2009-08-28 92cy23-76 figure 3.5.13 port7 (p76, p77) internal data bus s direction control (on bit basis) reset p7cr write p7 read low frequency clock p77 (xt2) s output latch p7 write (on by 1) s b selector a output buffer (open drain output) s direction control (on bit basis) p7cr write s output latch p7 write p7 read s b selector a output buffer (open drain output) p76 (xt1) enable signal for low fre q uenc y oscillato r
tmp92cy23/cd23a 2009-08-28 92cy23-77 port 7 register 7 6 5 4 3 2 1 0 bit symbol p77 p76 p74 p73 p72 p71 p70 read/write r/w r r/w reset state data from external port (output latch register is set to ?1?) data from external port data from external port (output latch register is set to ?1?) p7 (001ch) function ? ? ? 0(output latch register): pull-up resistor off 1(output latch register): pull-up resistor on port 7 control register 7 6 5 4 3 2 1 0 bit symbol p77c p76c p73c p72c p71c p70c read/write w w reset state 1 1 0 0 0 0 p7cr (001eh) function 0: input 1: output 0: input 1: output port 7 function register 7 6 5 4 3 2 1 0 bit symbol p74f p73f p72f p71f p70f read/write w reset state 0 0 0 0 0 p7fc (001fh) function 0: port 1: int0 0: port 1: srlub 0: port 1: srllb 0: port 1: srwr 0: port 1: rd note 1: when port p70 to p73 is used in the input mode, p7 register controls the built-in pull-up resistor. read-modify-write is prohibited in the input mode or the i/o mode. setting the built-in pull-up resistor may be depended on the states of the input pin. note 2: a read-modify-write operation cannot be performed in p7cr and p7fc registers. note 3: on using low-frequency resonator to p76, p77, it is necessary to set the following procedures to reduce the consumption power supply. ? connecting to a resonator p7cr ?11?, p7 ?00? ? connecting an oscillator p7cr ?11?, p7 ?10? figure 3.5.14 register for port 7
tmp92cy23/cd23a 2009-08-28 92cy23-78 3.5.7 port 8 (p80 to p83) ports 80 to 82 are 3-bit output ports, and port 83 is 1-bit i/o port. in addition to an output and an i/o port function, as for p80 and p81, a standard chip select signal output ( 0cs , 1cs ) and a 8-bit timer output (ta1out, ta3out), and p82 have a standard chip select signal output ( 2cs ), and p83 has the function of a standard chip select signal output ( 3cs ), a 8-bit timer output (ta5out), and a wait input ( wait ). these functions operate by setting the bit concerned of p8cr, p8fc, and p8fc2 register as ?1?. all bits of p8fc and p8fc2 are cleared to ?0? by the reset action, and p80 to p83 becomes an output port. moreover, the output latch of p82 is cleared to ?0? and the output latch of p80 to p81 and p83 is set to ?1?. (1) p80 ( 0cs , ta1out), p81 ( 1cs , ta3out) in addition to an output port function, ports p80 and p81 function as a standard chip select signal output ( 0cs , 1cs ) and a 8-bit timer output (ta1out, ta3out). figure 3.5.15 port 8 (p80, p81) a s selector b internal data bus function control (on bit basis) reset p8fc write p8 write p8 read p80 ( 0cs , ta1out) p81 ( 1cs , ta3out) function control2 (on bit basis) p8fc2 write s output latch s a selector b 0cs , 1cs ta1out, ta3out
tmp92cy23/cd23a 2009-08-28 92cy23-79 (2) p82 ( 2cs ) in addition to an output port function, a port p82 functions as a standard chip select signal output ( 2cs ). figure 3.5.16 port 8 (p82) a s selector b internal data bus function control (on bit basis) reset p8fc write p8 read p82 ( 2cs ) s output latch p8 write 2cs
tmp92cy23/cd23a 2009-08-28 92cy23-80 (3) p83( 3cs , wait , ta5out) in addition to an i/o port function, a port p83 functions as a standard chip select signal output ( 3cs ) and an 8-bit timer output (ta5out), and a wait input ( wait ). figure 3.5.17 port 8 (p83) s a selector b internal data bus function control (on bit basis) reset p8fc write p8cr write p8 read p83 ( wait 3cs , ta5out) function control2 (on bit basis) p8fc2 write s direction control (on bit basis) s a selector b 3cs p8 write s output latch s b selector a ta5out internal waitsignal
tmp92cy23/cd23a 2009-08-28 92cy23-81 port 8 register 7 6 5 4 3 2 1 0 bit symbol p83 p82 p81 p80 p8 (0020h) read/write r/w reset state data from external port (note1) 0 1 1 port 8 control register 7 6 5 4 3 2 1 0 bit symbol p83c p8cr (0022h) read/write w reset state 1 0: input 1: output port 8 function register 7 6 5 4 3 2 1 0 bit symbol p83f p82f p81f p80f p8fc (0023h) read/write w reset state 0 0 0 0 function 0 : port 1: wait , 3cs 0: port 1: 2cs 0: port 1: 1cs 0: port 1: 0cs port 8 function register 2 7 6 5 4 3 2 1 0 bit symbol p83f2 p81f2 p80f2 p8fc2 (0021h) read/write w w reset state 0 0 0 function 0: 1: ta5out 0: 1: ta3out 0: 1: ta1out 0 1 0 0 input port output port 0 1 reserved ta5out 1 0 wait 3cs 1 1 reserved reserved note 1: output latch register is set to ?1?. note 2: a read-modify-write operation cannot be performed in p8cr, p8fc and p8fc2 registers. note 3: when using p83 as a wait input, while setting it as p8cr = ?0?, p8fc = ?1?, it is necessary to set memory control register bxcs l or as ?011?. note 4: when setting a standard chip select signal ( 0cs to 3cs ) as an output, p8cr is set up after setting up p8fc. figure 3.5.18 register for port 8 wait , 3cs ,ta5out setting
tmp92cy23/cd23a 2009-08-28 92cy23-82 3.5.8 port c (pc0 to pc3) port c is a 4-bit input port. in addition to the input port function, port c has the input function (ta0in) of a 8-bit timer, and an external interrupt input function (int1 to int3). these functions operate by setting the bit concerned of pcfc register as ?1 ?. edge selection of ex ternal interrupt is set up in iimc2 and iimc3 register in an interrupt controller. all bits of pcfc are cleared to ?0? by the reset action, and all bits serve as an input port. (1) pc0 (ta0in) in addition to an i/o port function, a port pc0 has a function as a ta0in input of the timer channel 0. figure 3.5.19 port c (pc0) internal data bus ta0in pc read pc0(ta0in)
tmp92cy23/cd23a 2009-08-28 92cy23-83 (2) pc1 (int1), pc2 (int2), pc3 (int3) in addition to an input port function, port pc1 to pc3 has a function as an external interrupt input (int1 to int3). figure 3.5.20 port c (pc1, pc2 and pc3) internal data bus function control (on bit basis) reset pcfc write pc read pc1 (int1) pc2 (int2) pc3 (int3) int1 int2 int3 select level/edge and select rising/falling iimc2 iimc3
tmp92cy23/cd23a 2009-08-28 92cy23-84 port c register 7 6 5 4 3 2 1 0 bit symbol pc3 pc2 pc1 pc0 pc (0030h) read/write r reset state data from external port port c function register 7 6 5 4 3 2 1 0 bit symbol pc3f pc2f pc1f pc0f pcfc (0033h) read/write w reset state 0 0 0 0 function 0 : p o r t 1: int3 0: port 1: int2 0: port 1: int1 0: port 1: ta0in note1: a read-modify-write operation cannot be performed in pcfc register. note2: pc0 is not based on a functional setup of a port, but is inputted into ta0in of a 8-bit timer (tmra0). figure 3.5.21 register for port c
tmp92cy23/cd23a 2009-08-28 92cy23-85 3.5.9 port d (pd0 to pd4) port d is 4-bit i/o port (pd0, pd2 to pd4) and 1-bit input port (pd1). there are i/o of the serial channel 2, i/ o of a 16-bit timer (tmrb0, tmrb1), and an external interrupt input (int4 to int7) function in addition to an i/o port function. these functions operate by setting the bit concerned of pdcr, pdfc and pdfc2 register as ?1?. edge selection of external interrupt is set up in iimc2 and iimc3 register in an interrupt controller. all bits of pdcr, pd fc and pdfc2 are cleared to ?0? by the reset action, and all bits serve as an input port. (1) pd0 (int4, tb0out0) in addition to an i/o port function, a port pd0 has a function as a 16-bit timer output (tb0out0) and an external interrupt input (int4). figure 3.5.22 register for port d (pd0) internal data bus direction control (on bit basis) reset pdcr write pd write pd read pd0 (int4, tb0out0) function control (on bit basis) pdfc write r output latch s a selector b int4 tb0out0 select level/edge and select rising/falling iimc2 iimc3 s b selector a
tmp92cy23/cd23a 2009-08-28 92cy23-86 (2) pd1 (int5,tb1in0) in addition to the input port function, the port pd1 has a function as a 16-bit timer input (tb1in0) and an external interrupt input (int5). in a port setup, when choosing a 16-bit timer input and performing capture co ntrol, int5 disregards a setup of iimc2 and iimc3 registers, and operates according to a setup of tb1mod . figure 3.5.23 port d (pd1) internal data bus function control (on bit basis) pdfc write pd read pd1 (int5,tb1in0) function control2 (on bit basis) pcfc2 write select level/edge and select rising/falling iimc2 iimc3 tb1in0 int5 reset
tmp92cy23/cd23a 2009-08-28 92cy23-87 (3) pd2 (int6, tb1in1, txd2) in addition to the i/o port, pd2 has a function as a 16-bit timer input (tb1in1), an external interrupt input (int6), and a txd output (txd2) of the serial channel 2. when using this port as txd output (txd2), it can be set as open drain. in a port setup, when choosing a 16-bit ti mer input and performing capture control, int6 disregards a setup of iimc2 and iimc 3 registers, and operates according to a setup of tb1mod . figure 3.5.24 port d (pd2) internal data bus direction control (on bit basis) reset pdcr write pd read pd2 (int6, tb1in1,txd2) pdfc2 write function control2 (on bit basis) s b selector a function control (on bit basis) pdfc write int6 s a selector b txd2 r output latch pd write select level/edge and select rising/falling iimc2 iimc3 tb1in1 open drain possible = ?11?, = ?1?
tmp92cy23/cd23a 2009-08-28 92cy23-88 (4) pd3 (int7, tb1out0, rxd2) in addition to the i/o port function, the portd3 has a function as a 16-bit timer output (tb1out0), an external interrupt in put (int7), and a rxd input (rxd2) of the serial channel 2. figure 3.5.25 port d (pd3) internal data bus direction control (on bit basis) reset pdcr write pd read pd3 (int7, tb1out0,rxd2) pdfc2 write function control2 (on bit basis) s b selector a function control (on bit basis) pdfc write int7 s a selector b tb1out0 r output latch pd write select level/edge and select rising/falling iimc2 iimc3 rxd2
tmp92cy23/cd23a 2009-08-28 92cy23-89 (5) pd4 (tb1out1, sclk2, 2cts ) in addition to the i/o port function, pd 4 has a function as a 16-bit timer output (tb1out1), sclk i/o (sclk2) of the serial channel 2, or a cts input ( 2cts ). figure 3.5.26 port d (pd4) internal data bus direction control (on bit basis) reset pdcr write pd read pdfc2 write function control2 (on bit basis) s a selector b function control (on bit basis) pdfc write tb1out1 s a selector b pd4 (tb1out1,sclk2, 2cts ) r output latch pd write sclk2, 2cts sclk2 s a selector b
tmp92cy23/cd23a 2009-08-28 92cy23-90 port d register 7 6 5 4 3 2 1 0 bit symbol pd4 pd3 pd2 pd1 pd0 pd (0034h) read/write r/w r r/w reset state data from external port (note1) data from external port data from external port (note1) port d control register 7 6 5 4 3 2 1 0 bit symbol pd4c pd3c pd2c pd0c pdcr (0036h) read/write w reset state 0 0 0 0 function 0: input 1: output 0: input 1: output port d function register 7 6 5 4 3 2 1 0 bit symbol pd4f pd3f pd2f pd1f pd0f pdfc (0037h) read/write w reset state 0 0 0 0 0 function refer to following table port d function register 2 7 6 5 4 3 2 1 0 bit symbol pd4f2 pd3f2 pd2f2 pd1f2 pdfc2 (0035h) read/write w reset state 0 0 0 0 function refer to following table pd4 to pd0 function setting pd4 pd3 pd2 pd1 (note 3) pd0 (note 4) 0 , 0 , 0 input port input port input port input port input port 0 , 0 , 1 output port output port output port output port 0 , 1 , 0 reserved rxd2 tb1in1 tb1in0 int4 0 , 1 , 1 tb1out1 tb1out0 txd2(3-state) tb0out0 1 , 0 , 0 sclk2, 2cts input int7 int6 int5 1 , 0 , 1 sclk2 output reserved reserved 1 , 1 , 0 reserved reserved reserved reserved 1 , 1 , 1 reserved reserved txd2(o.d) note : , and are the bits x of pdfc2,pdfc and pdcr registers. note 1: output latch register is cleared to ?0?. note 2: there is no output latch register in pd1. note 3: a read-modify-write operation cannot be performed in pdcr, pdfc and pdfc2 registers. note 4: tb1in0 and tb1in1 input is inputted into the 16-bit timer tmrb1 irrespective of a functional setup of a port. note 5: rxd2, sclk2 input, and 2cts input are inputted into the serial channel 2 irrespective of a functional setup of a port. note 6: pd2 does not have a register for 3-state/open drain setup. moreover, there is no open drain function at the time of an output port. figure 3.5.27 register for port d
tmp92cy23/cd23a 2009-08-28 92cy23-91 3.5.10 port f (pf0 to pf5) port f is a 6-bit general-purpose i/o ports. all bits of pfcr, pffc and pffc2 are cleared to ?0? by the reset action, and all bits serve as an input port. in addition to an i/o port, there are i/o of th e serial channels 0 and 1, high speed serial channel (note) and an internal clock output function. these functions operate by setting the bit concerned of pfcr, pffc, pffc2, hscsel register as ?1?. all bits of pfcr, pffc, pffc2 and hscsel are cleared to ?0? by the re set action, and all bits serve as an input port. note: the high speed serial channel func tion is not built into tmp92cy23. (1) port f0 (txd0) in addition to an i/o port function, pf0 have a function as an output (txd0) of the serial channels 0. moreover, when using it as a txd output terminal, the output buffer has the open drain function in which a program is possible. an open drain function can be set up by the pffc , pfcr register. figure 3.5.28 port f (pf0) internal data bus direction control (on bit basis) reset pfcr write pf write pf read pf0 (txd0) function control (on bit basis) pffc write r output latch s b selector a s a selector b txd0 open drain possible = ? 10?
tmp92cy23/cd23a 2009-08-28 92cy23-92 (2) pf1(rxd0) in addition to the i/o port, pf1 have a function as an input (rxd0) of the serial channels 0. figure 3.5.29 port f (pf1) internal data bus direction control (on bit basis) reset pfcr write pf write pf read pf1 (rxd0) function control (on bit basis) pffc write r output latch s b selector a rxd0
tmp92cy23/cd23a 2009-08-28 92cy23-93 (3) pf2 ( cts0 , sclk0, clk) in addition to the i/o port, pf2 has a function as the cts input ( cts0 ), sclk i/o (sclk0), and the internal clock output (clk) of the serial channel 0. figure 3.5.30 port f (pf2) internal data bus direction control (on bit basis) reset pfcr write pf read pffc2 write function control2 (on bit basis) s a selector b function control (on bit basis) pffc write sclk0 output s a selector b pf2 (sclk0, 0cts ,clk) r output latch pf write sclk0, 0cts input clk output s b selector a
tmp92cy23/cd23a 2009-08-28 92cy23-94 (4) port f3 (txd1, hsso) in addition to an i/o port function, pf3 have a function as an output (txd1) of the serial channels 1 and output (hsso) of the high speed serial channels (note) . moreover, when using it as a txd output terminal, the output buffer has the open drain function in which a program is possible. an open drain function can be set up by the pffc , pfcr register. note: hsso output function is not built into tmp92cy23. figure 3.5.31 port f (pf3) direction control (on bit basis) reset pfcr write pf write pf read pf3 (txd1 hsso) function control (on bit basis) pffc write r output latch s b selector a s a selector b txd1 open drain possible = ? 10? uart/hsc control hscsel write s a selector b hsso internal data bus
tmp92cy23/cd23a 2009-08-28 92cy23-95 (5) pf4(rxd1, hssi) in addition to the i/o port, pf4 have a function as an input (rxd1) of the serial channels 0 and input (hssi) of high speed serial channels (note) . note: hssi input function is not built into tmp92cy23. figure 3.5.32 port f (pf4) direction control (on bit basis) reset pfcr write pf write pf read pf4 (rxd1, hssi) function control (on bit basis) pffc write r output latch s b selector a rxd1 uart/hsc control hscsel write s b selector a hssi internal data bus
tmp92cy23/cd23a 2009-08-28 92cy23-96 (6) pf5 ( cts1 , sclk1, hsclk) in addition to the i/o port function, pf5 has a function as the input ( cts1 ) or i/o (sclk1) of the serial channel 1 and output (hsclk) of high speed serial channels (note) . note: hsclk output function is not built into tmp92cy23. figure 3.5.33 port f (pf5) direction control (on bit basis) reset pfcr write pf write pf read pf5 (sclk1, cts1 , hsclk ) function control (on bit basis) pffc write r output latch s b selector a s a selector b sclk1 output uart/hsc control hscsel write s a selector b hsclk output cts1 sclk1 input internal data bus
tmp92cy23/cd23a 2009-08-28 92cy23-97 port f register 7 6 5 4 3 2 1 0 bit symbol pf5 pf4 pf3 pf2 pf1 pf0 pf (003ch) read/write r/w reset state data from external port (output latch register is cleared to ?0?) port f control register 7 6 5 4 3 2 1 0 bit symbol pf5c pf4c pf3c pf2c pf1c pf0c pfcr (003eh) read/write w reset state 0 0 0 0 0 0 function 0: input 1: output port f functon register 7 6 5 4 3 2 1 0 bit symbol pf5f pf4f pf3f pf2f pf1f pf0f pffc (003fh) read/write w reset state 0 0 0 0 0 0 function 0: port 1: sclk1 1cts 0: port 1: rxd1 0: port 1: txd1 0: port 1: sclk0 0cts 0: port 1: rxd0 0: port 1: txd0 port f functon register 2 7 6 5 4 3 2 1 0 bit symbol pf2f2 pffc2 (003dh) read/write w reset state 0 function 0: 1: clk sio1/ hsc control register 7 6 5 4 3 2 1 0 bit symbol ? ? ? ? ? ? ? siocnt hscsel (00f4h) read/write r r/w reset state 0 0 0 0 0 0 0 0 function 0 : s i o 1 1: hsc note: hscsel register is not built into tmp92cy23.
tmp92cy23/cd23a 2009-08-28 92cy23-98 pf5 to pf0 function setting pf2 pf1 pf0 0 , 0 , 0 input port input port input port 0 , 0 , 1 output port output port output port 0 , 1 , 0 sclk0, 0cts input rxd0 input txd0 (o.d output) 0 , 1 , 1 sclk0 output reserved txd0 (3-state) 1 , 0 , 0 reserved 1 , 0 , 1 clk output 1 , 1 , 0 reserved 1 , 1 , 1 reserved pf5 pf4 pf3 0 , 0 , 0 input port input port input port 0 , 0 , 1 output port output port output port 0 , 1 , 0 sclk1, 1cts input rxd1 input txd1 (o.d output) 0 , 1 , 1 sclk1 output reserved txd1 (3-state) 1 , 0 , 0 reserved reserved reserved 1 , 0 , 1 reserved reserved reserved 1 , 1 , 0 reserved hssi input (note) reserved 1 , 1 , 1 hsclk output (note) reserved hsso (3-state) (note) note : , and are the bits x of pffc2,pffc and pfcr registers. note 1: a read-modify-write operation cannot be performed in pdcr, pdfc and pdfc2 registers. note 2: pf0 and pf3 does not have a register for 3-state/ open drain setup. moreover, there is no open drain function at the time of an output port. note3: hsso,hssi and hsclk functions are not built into tmp92cy23. figure 3.5.34 register for port f
tmp92cy23/cd23a 2009-08-28 92cy23-99 3.5.11 port g (pg0 to pg7) port g is 8-bit general-purpose input ports. in addition to an input port function, there are an analog input for ad converters (an0 to an7) and a key input (ki0 to ki7) function for a key on wake up. these functions operate by setting the bit concerned of pgfc, kien register as "1". moreover, edge selection of a key input is set up by the kicr register. by the reset action, all bits of pgfc are set to ?1?, and all bits of kien are cleared to ?0?, and it becomes all bit analog input ports (port input disable). a key input is enabled by the kien register, and when the edge chosen in the kicr register is detected, the key on wake up in put kwi occurs. although a key on wake up input can release all halt mode states , there is no function as interrupt. figure 3.5.35 port g internal data bus pg to pg7 (ki0 to ki7) kwi rising/falling edge detection function control (on bit basis) pgfc write pg read reset pg0 to pg7 8 input or kei input rising/falling control ( on bit basis ) kicr write reset key input enable (on bit basis) kien write reset adreg read ad converter channel selector conversion result register
tmp92cy23/cd23a 2009-08-28 92cy23-100 port g register 7 6 5 4 3 2 1 0 bit symbol pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 pg (0040h) read/write r reset state data from external port (note1) port g function register 7 6 5 4 3 2 1 0 bit symbol pg7f pg6f pg5f pg4f pg3f pg2f pg1f pg0f pgfc (0043h) read/write w reset state 1 1 1 1 1 1 1 1 function 0: analog input 1: input port/key input key input enable register 7 6 5 4 3 2 1 0 bit symbol ki7en ki6en ki5en ki4en ki3en ki2en ki1en ki0en kien (13a0h) read/write w reset state 0 0 0 0 0 0 0 0 function ki7 input 0: disable 1: enable ki6 input 0: disable 1: enable ki5 input 0: disable 1: enable ki4 input 0: disable 1: enable ki3 input 0: disable 1: enable ki2 input 0: disable 1: enable ki1 input 0: disable 1: enable ki0 input 0: disable 1: enable key input control register 7 6 5 4 3 2 1 0 bit symbol ki7edge ki6edge ki5edge ki4edge ki3edge ki2edge ki1edge ki0edge kicr (13a1h) read/write w reset state 0 0 0 0 0 0 0 0 function ki7 edge 0: rising 1: falling ki6 edge 0: rising 1: falling ki5 edge 0: rising 1: falling ki4 edge 0: rising 1: falling ki3 edge 0: rising 1: falling ki2 edge 0: rising 1: falling ki1 edge 0: rising 1: falling ki0 edge 0: rising 1: falling pg7 to pg0 function setting 0 1 0 input port analog input 1 key input reserved note : and are the bits x of pgfc and kien registers. note 1: it operates as an analog input port (input port disable). note 2: a read-modify-write operation cannot be performed in pgfc,kien and kicr registers. note 3: the input channel selection of the ad conb erter is set by ad mode control register admod1. figure 3.5.36 register for port g
tmp92cy23/cd23a 2009-08-28 92cy23-101 3.5.12 port l (pl0 to pl3) port l is a 4-bit input port. in addition to an input port function, port l has the analog input function of an ad converter. moreover, pl3 has the adtrg function of an ad converter. when you use pl3 as an adtrg , set plfc as ?0?. all bits of a plfc register are set to ?1? by the reset action, and port l become analog input port (port input disable). figure 3.5.37 port l internal data bus adtrg (pl3 only) pl read pl0(an8) pl1(an9) pl2(an10) pl3(an11, adtrg ) ad converter channel selector ad read conversion result register function control (on bit basis) plfc write reset
tmp92cy23/cd23a 2009-08-28 92cy23-102 port l register 7 6 5 4 3 2 1 0 bit symbol pl3 pl2 pl1 pl0 pl (0054h) read/write r reset state data from external port (note1) port l function register 7 6 5 4 3 2 1 0 bit symbol pl3f pl2f pl1f pl0f plfc (0057h) read/write w reset state 1 1 1 1 function 0: analog input 1:input port (note3) note 1: it operates as an analog input port (input port disable). note 2: a read-modify-write operation cannot be performed in plfc register. note 3: the input channel selectino of the ad conver ter is set by ad mode control register admod1. moreover, a set up of ad trigger ( adtrg ) input permission is set by admod2. figure 3.5.38 register for port l
tmp92cy23/cd23a 2009-08-28 92cy23-103 3.5.13 port n (pn0 to pn5) port n is 6-bit general-purpose i/o ports. mo reover, pn1, pn2, pn4, and pn5 serve as an open drain output, when it is set as an output. there are the following functions in addition to an i/o port. ? the i/o function of the serial bus interface 0 (sck0, so0/sda0, si0/scl0) ? the i/o function of the serial bus interface 1 (sck1, so1/sda1, si1/scl1) these functions operate by setting the bit concerned of pncr, pnfc register as ?1?. all bits of pncr and pnfc are cleared to ?0? by the reset action, and all bits serve as an input port. moreover, all bits of an output latch are set to ?1?. (1) pn0 (sck0), pn3 (sck1) pn0 and pn3 are general-purpose i/o ports. it is also used as a sck (clock i/o signal in sio mode). figure 3.5.39 port n (pn0, pn3) internal data bus direction control (on bit basis) reset pncr write pn write pn read pn0(sck0) pn3(sck1) function control (on bit basis) pnfc write s output latch s b selector a sck0 input sck1 input s a selector b sck0 output sck1 out p ut
tmp92cy23/cd23a 2009-08-28 92cy23-104 (2) pn1 (sda0/so0), pn4 (sda1/so1) pn1 and pn4 are general-purpose i/o ports. it is also used as a so (data output signal in sio mode), and sda (data signal in i 2 cbus mode). moreover, these ports serve as an open drain output. figure 3.5.40 port n (pn1, pn4) internal data bus direction control (on bit basis) reset pncr write pn write pn read pn1(sda0,so0) pn4(sda1,so1) function control (on bit basis) pnfc write s output latch s b selector a sda0/sda1 input s a selector b sda0/sda1 output so0/so1 out p ut output buffer (open drain output)
tmp92cy23/cd23a 2009-08-28 92cy23-105 (3) pn2 (scl0/si0), pn5 (scl1/si1) pn2 and pn5 are general-purpose i/o ports. it is also used as a si (data input signal in sio mode), and scl (clock signal in i 2 cbus mode). moreover, these ports serve as an open drain output. figure 3.5.41 port n (pn2, pn5) internal data bus direction control (on bit basis) reset pncr write pn write pn read pn2(scl0,si0) pn5(scl1,si1) function control (on bit basis) pnfc write s output latch s b selector a si0/si1 input scl0/scl1 input s a selector b scl0/scl1 out p ut output buffer (open drain output)
tmp92cy23/cd23a 2009-08-28 92cy23-106 port n register 7 6 5 4 3 2 1 0 bit symbol pn5 pn4 pn3 pn2 pn1 pn0 pn (005ch) read/write r/w reset state data from external por t (output latch register is set to ?1?) port n control register 7 6 5 4 3 2 1 0 bit symbol pn5c pn4c pn3c pn2c pn1c pn0c pncr (005eh) read/write w reset state 0 0 0 0 0 0 function 0: input 1: output port n function register 7 6 5 4 3 2 1 0 bit symbol pn5f pn4f pn3f pn2f pn1f pn0f pnfc (005fh) read/write w reset state 0 0 0 0 0 0 function 0: port 1: si1, scl1 0: port 1: so1,sda1 0: port 1: sck1 0: port 1: si0, scl0 0: port 1: so0,sda0 0: port 1: sck0 pn5 to pn0 function setting pn5 pn4 pn3 pn2 pn1 pn0 0 , 0 , 0 input port input port input port input port input port input port 0 , 0 , 1 output port output port output port output port output port output port 0 , 1 , 0 si1 input so1 output sck1 input si0 input so0 output sck0 input 0 , 1 , 1 scl1 input/output sda1 input/output sck1 output scl0 input/output sda0 input/output sck0 output note : and are the bits x of pnfc and pncr registers. note 1: a read-modify-write operation cannot be performed in pnfc and pncr registers. figure 3.5.42 register for port n
tmp92cy23/cd23a 2009-08-28 92cy23-107 3.6 memory controller 3.6.1 functional overview the tmp92cy23/cd23a has a memory contro ller with a following features to control four programmable address spaces: (1) four programmable address spaces the memc can specify a start address and a block size for each of he four memory spaces. ? sram or rom: all cs spaces (cs0 to cs3) can be assigned. ? page-rom: only the cs2 space can be assigned. (2) memory specification the memc can specify the type of memory, sram or rom, to associate with the selected address spaces. (3) data bus size specification the data bus width is selectable from 8 an d 16 bits for the respective chip select spaces. (4) wait control the number of wait states to be inserted in to an external bus cycle is determined by the wait state bits of the control register and the wait input pin. the number of wait states of a read cycle and that of a write cycle can be specified individually. the number of wait states can be selected from the following 6 options. 0 wait state, 1 wait state, 2 wait states, 3 wait states, 4 wait states n wait states (controlled by the wait pin)
tmp92cy23/cd23a 2009-08-28 92cy23-108 3.6.2 control registers and memory access operations after reset this section describes the regi sters to control the memory co ntroller, their reset states and the necessary settings after reset. (1) control registers the control registers of the memory controller are listed below. ? control registers: bncsh/bncsl (n = 0 to 3, ex) configures the basic settings of the memory controller, such as the memory type, specification and the number of wait states to be inserted into a read or write cycle. ? memory start address register: msarn (n = 0 to 3) specifies a start a ddress for a selected address space. ? memory address mask register: mamr (n = 0 to 3) specifies a block size for a selected address space. ? page rom control register: pmemcr selects a method of accessing page-rom. (2) memory access opera tions after reset upon reset, only the control registers (b2csh and b2csl) for the cs2 space automatically becomes effective. then, the bus width specification bits of the control register for the cs2 space becomes undefined, this bit mu st be set before accessing the external cs2 spaces. at the same time, the address range eb tween 000000h and ffffffh is defined as the cs2 space (the b2csh is cleared to ?0?). then, the address spaces are configured by msarn and mamrn. the bncsh and bncsl registers are also set up. the bncsh must be set to ?1? to enable these settings.
tmp92cy23/cd23a 2009-08-28 92cy23-109 3.6.3 basic functions and register settings this section describes some of the memory controller f unctions, such as setting the address range for each address space, associating memory to the selected and setting the number of wait states to be inserted. (1) programming chip select spaces the address space is specified by two registers. the memory start address re gister (msarn) sp ecify the start address for the cs spaces. the memory controller compares the register value and the address every bus cycle. the address bit which is masked by the mamrn is not compared by the memory controller. the cs spaces size is determ ined by setting the memory address mask register. the set value in the register is compared with the cs spaces on the bus. if the result is a match, the memory contro ller sets the chip select signal ( csn ) to ?low?. (i) memory start a ddress registers the msar0 to msar3 specify the start addresses for the cs0 to cs3 spaces. the bits specify the upper 8 bi ts (a23 to a16) of the start address. the lower 16 bits of the start addre ss (a15 to a0) are assumed to be 0000h. accordingly, the start address can only be a multiple of 64 kbytes, ranging from 000000h to ff0000h. (ii) memory address mask registers the memory address mask register determines whether an address bit is compared or not. in register setting, ?0? is ?compare?, and ?1? is ?do not compare?. the address bits that can be set depends on the cs spaces. cs0: a20 to a8 cs1: a21 to a8 cs2 to cs3: a22 to a15 the upper bits are always compared. the cs space size is determined by the result of the comparison. the size to be set depending on the cs space is as follows. size (bytes) cs area 256 512 32 k 64 k 128 k 256 k 512 k 1 m 2 m 4 m 8 m cs0 cs1 cs2 to cs3 note: after reset, only the control register for the cs2 spac e is effective. the control register for the cs2 space has the b2m bit. if the b2m bit is cleared to ?0?, t he address range between 000000h and ffffffh is defined as the cs2 space. (the b2m bit is cleared to ?0? after rese t.) by setting the b2csh bit to ?1?, the start address and the block size can be arbitraril y specified, as in the other spaces.
tmp92cy23/cd23a 2009-08-28 92cy23-110 (iii) example of register setting to set the cs1 space 512 bytes from address 110000h, set the register as follows. msar1 register 7 6 5 4 3 2 1 0 bit symbol m1s23 m1s22 m1s21 m1s20 m1s19 m1s18 m1s17 m1s16 specified value 0 0 0 1 0 0 0 1 m1s23 to m1s16 bits of the msar1 correspond to address a23 to a16. a15 to a0 are cleared to ?0?. therefore, if msar1 is set to the above mentioned value, the start address of the cs space is set to address 110000h. mamr1 register 7 6 5 4 3 2 1 0 bit symbol m1v21 m1v20 m1v19 m1v18 m1v17 m1v16 m1v15 to m1v9 m1v8 specified value 0 0 0 0 0 0 0 1 m1v21 to m1v16 and m1v8 bits of the mamr1 are set whether addresses a21 to a16 and a8 are compared or not. in regi ster setting, ?0? is ?compare?, and ?1? is ?do not to compare?. m1v15 to m1v9 bits determine whether addresses a15 to a9 are compared or not with bit 1. a23 and a22 are always compared. when set as above, a23 to a9 are compared with the values that is set as the start addresses. therefore, the 512 byte s (addresses 110000h to 1101ffh) are set as cs1 spaces. if it is compared with the addresses on the bus, the chip select signal cs1 is set to ?low?. a23 to a21 are always compared with cs0 spaces. whether a20 to a8 are compared or not is determined by the register. similarly, a23 is always compared with cs2 space to cs3 space. whether a22 to a15 are compared or not is determined by the register. note: when the specified address space ov erlaps with the on- chip memory area, priority oreder of address spaces are as follows. on-chip i/o > on-chip memory > cs0 space > cs1 space > cs2 space > cs3 space the bexcsl and bexcsh registers specify the data bus width and number of wait states when an address outside the cs0 to cs3 spaces ( csex space) is accessed. these registers are always enabled for the csex space.
tmp92cy23/cd23a 2009-08-28 92cy23-111 (2) memory specification setting the bits specifies the memory type that is associated with each address spaces. the interface signal that corresponds to the specified memory type is generated. the memory type is specified as follows: bit (bncsh register) bnom1 bnom0 memory type 0 0 sram/rom (default) 0 1 reserved 1 0 reserved 1 1 reserved (3) data bus width specification the data bus width can be specifie d for each address space by the bncsh bits as follows. bit (bncsh register) bnbus1 bnbus0 bus width 0 0 8-bit bus mode (note 2) 0 1 16-bit bus mode 1 0 reserved 1 1 reserved as described above, the tmp92cy23/cd23 a supports dinamic bus sizing, which allows the controller to transfer operands to or from the selected address spaces while automatically determining the data bus width. on which part of the data bus the data is actually placed is determined by the data size, bus width and start address. the table below provides a detailed description of the actual bus operation. note1: if two memories with different bus widths are assigned to consecutive addresses, do not execute an instruction that accesses the addresses crossing the boundary between those memories. otherwise, a read/write operation might not be performed correctly note2: upon reset, the bus width specification bits of t he control register for the cs 2 space (b2csh ) becomes undefined, this bit must be set bef ore accessing the external cs2 spaces.
tmp92cy23/cd23a 2009-08-28 92cy23-112 cpu data operand data size (bit) operand start address memory data size (bit) cpu address d32 to d24 d23 to d16 d15 to d8 d7 to d0 4n + 0 8/16 4n + 0 xxxxx xxxxx xxxxx b7 to b0 8 4n + 1 xxxxx xxxxx xxxxx b7 to b0 4n + 1 16 4n + 1 xxxxx xxxxx b7 to b0 xxxxx 4n + 2 8/16 4n + 2 xxxxx xxxxx xxxxx b7 to b0 8 4n + 3 xxxxx xxxxx xxxxx b7 to b0 8 4n + 3 16 4n + 3 xxxxx xxxxx b7 to b0 xxxxx (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 4n + 0 16 4n + 0 xxxxx xxxxx b15 to b8 b7 to b0 (1) 4n + 1 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 1 xxxxx xxxxx b7 to b0 xxxxx 4n + 1 16 (2) 4n + 2 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 4n + 2 16 4n + 2 xxxxx xxxxx b15 to b8 b7 to b0 (1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0 8 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 3 xxxxx xxxxx b7 to b0 xxxxx 16 4n + 3 16 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16 8 (4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 0 xxxxx xxxxx b15 to b8 b7 to b0 4n + 0 16 (2) 4n + 2 xxxxx xxxxx b31 to b24 b23 to b16 (1) 4n + 0 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 1 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 2 xxxxx xxxxx xxxxx b23 to b16 8 (4) 4n + 3 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 1 xxxxx xxxxx b7 to b0 xxxxx (2) 4n + 2 xxxxx xxxxx b23 to b16 b15 to b8 4n + 1 16 (3) 4n + 4 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 2 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 3 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 4 xxxxx xxxxx xxxxx b23 to b16 8 (4) 4n + 5 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 2 xxxxx xxxxx b15 to b8 b7 to b0 4n + 2 16 (2) 4n + 4 xxxxx xxxxx b31 to b24 b23 to b16 (1) 4n + 3 xxxxx xxxxx xxxxx b7 to b0 (2) 4n + 4 xxxxx xxxxx xxxxx b15 to b8 (3) 4n + 5 xxxxx xxxxx xxxxx b23 to b16 8 (4) 4n + 6 xxxxx xxxxx xxxxx b31 to b24 (1) 4n + 3 xxxxx xxxxx b7 to b0 xxxxx (2) 4n + 4 xxxxx xxxxx b23 to b16 b15 to b8 32 4n + 3 16 (3) 4n + 6 xxxxx xxxxx xxxxx b31 to b24 xxxxx: the input data placed on the data bus indicated by this symbol is i gnored during a read operation. during a write operation, the bus is in the high-impedance state, and the write strobe signal remains inactive.
tmp92cy23/cd23a 2009-08-28 92cy23-113 (4) wait control the external bus cycle completes in two states at minimum (100 ns at f sys = 20 mhz) without inserting a wait state. setting up the bncsl specifies the number of wait states to be inserted in a write cycle, and setting the bits specifies the number of wait states to be inserted in a read cycle. the external bus cycle can be programmed as follows; bncsl register / bnww2 bnww1 bnww0 bnwr2 bnwr1 bnwr0 number of wait states 0 0 1 2states (0 wait state), fixed wait-state mode 0 1 0 3states (1 wait state), fixed wait-state mode (default) 1 0 1 4states (2 wait states), fixed wait-state mode 1 1 0 5states (3 wait states), fixed wait-state mode 1 1 1 6states (4 wait states), fixed wait-state mode 0 1 1 wait pin input mode other than the above reserved (i) fixed wait-state mode the bus cycle is completed in the specified number of states. the number of states can be selected from 2 (0 wait state) through 6 (4 wait states). (ii) wait pin input mode in this mode, the wait signal is sampled. a wait state is continued to be inserted while the wait signal is sampled active. the minimum bus cycle in this mode is two states. the bus cycle is completed if the wait signal is non-active (?high? level) at the second states. the bus cycle is extended as the wait signal remains active after second states.
tmp92cy23/cd23a 2009-08-28 92cy23-114 (5) insert recovery cycle if the plural memory which data-output-floating-time (t df ) is long (the external rom and etc.) are set, it is necessary to consider each other?s t df times. however, if bncsh is set, you can insert dummy cycle of 1- state just before the first bus cycle which start accessing to other cs space. bncsh 0 no dummy cycle is inserted (default). 1 dummy cycle is inserted. ? when no dummy cycle is inserted (0 wait state) ? when a dummy cycle is inserted (0 wait state) clk address csm csn rd clk address csm csn rd dummy
tmp92cy23/cd23a 2009-08-28 92cy23-115 (6) basic bus timing ? external bus read/write bus cycle (0 wait state) ? external bus read/write bus cycle (1 wait state) clk (20mhz) t1 t2 clk (20mhz) address cs rd d15 to d0 srwr d15 to d0 input read write srxxb out p ut tw d15 to d0 address cs t1 t2 rd srwr d15 to d0 in p ut read write srxxb output
tmp92cy23/cd23a 2009-08-28 92cy23-116 ? external bus read/write cycle (0 wait state at wait pin input mode) ? external bus read/write cycle (n wait state at wait pin input mode) t1 tw t2 in p ut output write sampling sampling wait address cs rd d15 to d0 srwr d15 to d0 clk (20mhz) srxxb r ea d in p ut output read write wait sampling address cs rd d15 to d0 srwr d15 to d0 clk (20mhz) srxxb t2 t1
tmp92cy23/cd23a 2009-08-28 92cy23-117 ? example of wait input cycle (5 wait state) csn srwr rd wait d q ck res d q ck res d q ck res d q ck res d q ck res clk ff0 ff1 ff2 ff3 ff4 clk (20 mhz) 12 3 4 5 6 7 csn rd wait ff_res ff0_d ff0_q ff1_q ff2_q ff3_q
tmp92cy23/cd23a 2009-08-28 92cy23-118 3.6.4 controlling the page mode access to rom this section describes page mode access operations to rom and the required register settings. the page mode operation to rom is specified by pmemcr. (1) operations and register settings the tmp92cy23/cd23a supports page mode accesses to rom. only the cs2 space can be configured for this mode of access. the page mode operation to rom is specified by the page rom control register, pmemcr. setting the pmemcr bit to ?1? sets the mode of memory access to the cs space to page mode. the number of cycles required for a read cycle is specified by the pmemcr bits. pmemcr opwr1 opwr0 number of cycles in page mode 0 0 1 cycle (n-1-1-1 mode) (n 2) 0 1 2 cycle (n-2-2-2 mode) (n 3) 1 0 3 cycle (n-3-3-3 mode) (n 4) 1 1 reserved note: specify the number of wait state ?n? usi ng the control register (b2csl) for cs2 space. the page size (the number of bytes) of rom as seen from the cpu is determined by pmemcr. when the specified page boundary is reached, the controller terminates the page read operation. the first data of the next page is read in the normal mode. then, the following da ta is read again in page mode. pmemcr pr1 pr0 rom page size 0 0 64 bytes 0 1 32 bytes 1 0 16 bytes 1 1 8 bytes (2) signal timing pulse figure 3.6.1 timing pulse diagram (when using a 8-bit setting) t h a data in p ut data in p ut data in p ut data in p ut t cyc a 0 to a23 clk d0 to d15 rd cs2 + 0 + 1 + 2 + 3 t ad3 t ad2 t ad2 t ad2 t hr t h a t h a t h a t1
tmp92cy23/cd23a 2009-08-28 92cy23-119 3.6.5 list of registers the memory control registers and the settings are described as follows. for the addresses of the registers, see section 5 ?table of special function registers (sfrs)?. (1) control registers the control register is a pair of bncsl and bncsh. (?n? is a number of the cs space.) bncsl has the same configuration rega rdless of the cs space. in bncsh, only b2csh which is corresponded to the cs2 space has a different configuration from the others. bncsl 7 6 5 4 3 2 1 0 bit symbol bnww2 bnww1 bnww0 bnwr2 bnwr1 bnwr0 read/write w w reset state 0 1 0 0 1 0 specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = wait pin input mode others = (reserved) specifies the number of read waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = wait pin input mode others = reserved b2csh 7 6 5 4 3 2 1 0 bit symbol b2e b2m ? b2rec b2om1 b2om0 b2bus1 b2bus0 read/write w reset state 1 0 0 0 0 0 undefined undefined : enable bit 0 = no chip select signal output. 1 = chip select signal output (default). note: after reset, only the enable bit of b2cs register is valid (?1?). : cs space specification 0 = sets the cs2 space to addresses 000000h to ffffffh (default). 1 = sets the cs2 space to programmable. note: after reset, the cs2 space is set to addresses 000000h to ffffffh. : sets the dummy cycle for data output recovery time. 0 = not insert a dummy cycle (default). 1 = insert a dummy cycle. 00 = sram or rom (default) others = reserved sets the data bus width. 00 = 8 bits 01 = 16 bits 10 = reserved 11 = reserved note: the value of bit is set according to the state of am<1:0> pin after reset.
tmp92cy23/cd23a 2009-08-28 92cy23-120 bncsh (n = 0, 1, 3) 7 6 5 4 3 2 1 0 bit symbol bne bnrec bnom1 bnom0 bnbus1 bnbus0 read/write w w reset state 0 0 0 0 0 0 : enable bit 0 = no chip select signal output (default). 1 = chip select signal output. note: after reset, only the enable bit b2e of b2cs register is valid (?1?). : sets the dummy cycle for data output. 0 = not insert a dummy cycle (default). 1 = insert a dummy cycle. 00 = sram or rom (default) 01 = reserved 10 = reserved 11 = reserved sets the data bus width. 00 = 8 bits (default) 01 = 16 bits 10 = reserved 11 = reserved bexcsl 7 6 5 4 3 2 1 0 bit symbol bexww2 bexww1 bexww0 bexwr2 bexwr1 bexwr0 read/write w w reset state 0 1 0 0 1 0 specifies the number of write waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = wait pin input mode others = (reserved) specifies the number of read waits. 001 = 2 states (0 waits) access 010 = 3 states (1 wait) access 101 = 4 states (2 waits) access 110 = 5 states (3 waits) access 111 = 6 states (4 waits) access 011 = wait pin input mode others = reserved bexcsh 7 6 5 4 3 2 1 0 bit symbol bexrec bexom1 bexom0 bexbus1 bexbus0 read/write w reset state 0 0 0 0 0 00 = sram or rom (default) 01 = reserved 10 = reserved 11 = reserved 00 = 8 bits (default) 01 = 16 bits 10 = reserved 11 = reserved
tmp92cy23/cd23a 2009-08-28 92cy23-121 (2) block address register a start address and an address area of th e cs spaces are specified by the memory start address register (msarn) and the me mory address mask register (mamrn). the memory start address register sets all start address similarly regardless of the cs spaces. the bit to be set by the mamrn is depended on the cs spaces. msarn (n = 0 to 3) 7 6 5 4 3 2 1 0 bit symbol mns23 mns22 mns21 mns20 mns19 mns18 mns17 mns16 read/write r/w reset state 1 1 1 1 1 1 1 1 sets a start address. sets the start address of the cs spaces. are corresponding to the address a23 to a16. mamr0 7 6 5 4 3 2 1 0 bit symbol m0v20 m0v19 m0v18 m0v17 m0v16 m0v15 m0v14 to m0v9 m0v8 read/write r/w reset state 1 1 1 1 1 1 1 1 enables or masks comparison of the addresses. are corresponding to addresses a20 to a8. are corresponding to address a14 to a9 by 1 bit. if ?0? is set, the comparison between the value of the address bus and the start address is enabled. if ?1? is set, the comparison is masked. mamr1 7 6 5 4 3 2 1 0 bit symbol m1v21 m1v20 m1v19 m1v18 m1v17 m1v16 m1v15 to m1v9 m1v8 read/write r/w reset state 1 1 1 1 1 1 1 1 enables or masks comparison of the addresses. are corresponding to addresses a21 to a8. are corresponding to address a15 to a9 by 1 bit. if ?0? is set, the comparison between the value of the address bus and the start address is enabled. if ?1? is set, the comparison is masked.
tmp92cy23/cd23a 2009-08-28 92cy23-122 mamrn (n = 2 to 3) 7 6 5 4 3 2 1 0 bit symbol mnv22 mnv21 mnv20 mnv19 mnv18 mnv17 mnv16 mnv15 read/write r/w reset state 1 1 1 1 1 1 1 1 enables or masks comparison of the addresses. are corresponding to addresses a22 to a15. if ?0? is set, the comparison between the value of the address bus and the st art address is enabled. if ?1? is set, the comparison is masked. after a reset, masr0 to msar3 and msar0 to mamr3 are set to ?ffh?. b0csh, b1csh, and b3csh are reset to ?0?. this disabling the cs0, cs1, and cs3 areas. however, b2csh< b2m> is reset to ?0? and b2csh to ?1?, and cs2 is enabled 000000h to ffffffh . also the bus width and number of waits specified in bexcsh/l are used for accessing address except the specified cs0 to cs3 area.
tmp92cy23/cd23a 2009-08-28 92cy23-123 (3) page rom control register (pmemcr) the page rom control register sets page rom accessing. rom page accessing is executed only in cs2 space. pmemcr 7 6 5 4 3 2 1 0 bit symbol opge opwr1 opwr0 pr1 pr0 read/write r/w reset state 0 0 0 1 0 enable bit 0 = no rom page mode accessing (default) 1 = rom page mode accessing specifies the number of waits. 00 = 1 state (n-1-1-1 mode) (n 2) (default) 01 = 2 states (n-2-2-2 mode) (n 3) 10 = 3 states (n-3-3-3 mode) (n 4) 11 = reserved note: set the number of waits ?n? to the control register (bncsl) in cs spaces. rom page size 00 = 64 bytes 01 = 32 bytes 10 = 16 bytes (default) 11 = 8 bytes
tmp92cy23/cd23a 2009-08-28 92cy23-124 table 3.6.1 control register (1/2) 7 6 5 4 3 2 1 0 b0csl bit symbol b0ww2 b0ww1 b0ww0 b0wr2 b0wr1 b0wr0 (0140h) read/write w w reset state 0 1 0 0 1 0 b0csh bit symbol b0e ? ? b0rec b0om1 b0om0 b0bus1 b0bus0 (0141h) read/write w reset state 0 0 (note1) 0 (note1) 0 0 0 0 0 mamr0 bit symbol m0v20 m0v19 m0v18 m0v17 m0v16 m0v15 m0v14-v9 m0v8 (0142h) read/write r/w reset state 1 1 1 1 1 1 1 1 msar0 bit symbol m0s23 m0s22 m0s21 m0s20 m0s19 m0s18 m0s17 m0s16 (0143h) read/write r/w reset state 1 1 1 1 1 1 1 1 b1csl bit symbol b1ww2 b1ww1 b1ww0 b1wr2 b1wr1 b1wr0 (0144h) read/write w w reset state 0 1 0 0 1 0 b1csh bit symbol b1e ? ? b1rec b1om1 b1om0 b1bus1 b1bus0 (0145h) read/write w reset state 0 0 (note1) 0 (note1) 0 0 0 0 0 mamr1 bit symbol m1v21 m1v20 m1v19 m1v18 m1v17 m1v16 m1v15-v9 m1v8 (0146h) read/write r/w reset state 1 1 1 1 1 1 1 1 msar1 bit symbol m1s23 m1s22 m1s21 m1s20 m1s19 m1s18 m1s17 m1s16 (0147h) read/write r/w reset state 1 1 1 1 1 1 1 1 b2csl bit symbol b2ww2 b2ww1 b2ww0 b2wr2 b2wr1 b2wr0 (0148h) read/write w w reset state 0 1 0 0 1 0 b2csh bit symbol b2e b2m ? b2rec b2om1 b2om0 b2bus1 b2bus0 (0149h) read/write w reset state 1 0 0 (note1) 0 0 0 note3 note3 mamr2 bit symbol m2v22 m2v21 m2v20 m2v19 m2v18 m2v17 m2v16 m2v15 (014ah) read/write r/w reset state 1 1 1 1 1 1 1 1 msar2 bit symbol m2s23 m2s22 m2s21 m2s20 m2s19 m2s18 m2s17 m2s16 (014bh) read/write r/w reset state 1 1 1 1 1 1 1 1 b3csl bit symbol b3ww2 b3ww1 b3ww0 b3wr2 b3wr1 b3wr0 (014ch) read/write w w reset state 0 1 0 0 1 0 b3csh bit symbol b3e ? ? b3rec b3om1 b3om0 b3bus1 b3bus0 (014dh) read/write w reset state 0 0 (note) 0 (note) 0 0 0 0 0 mamr3 bit symbol m3v22 m3v21 m3v20 m3v19 m3v18 m3v17 m3v16 m3v15 (014eh) read/write r/w reset state 1 1 1 1 1 1 1 1 msar3 bit symbol m3s23 m3s22 m3s21 m3s20 m3s19 m3s18 m3s17 m3s16 (014fh) read/write r/w reset state 1 1 1 1 1 1 1 1
tmp92cy23/cd23a 2009-08-28 92cy23-125 table 3.6.2 control register (1/2) 7 6 5 4 3 2 1 0 bexcsh bit symbol bexrec bexom1 bexom0 bexbus1 bexbus0 (0159h) read/write w reset state 0 0 0 0 0 bexcsl bit symbol bexww2 bexww1 bexww0 bexwr2 bexwr1 bexwr0 (0158h) read/write w w reset state 0 1 0 0 1 0 pmemcr bit symbol opge opwr1 opwr0 pr1 pr0 (0166h) read/write r/w reset state 0 0 0 1 0 note 1: always write ?0?. note 2: a read-modify-write operation cannot be perfor med in bncsl, bncsh registers (n=0 to 3, ex). note3: upon reset, these bits become undefined, th is bit must be set before accessing the cs2 spaces.
tmp92cy23/cd23a 2009-08-28 92cy23-126 3.6.6 notes (1) timing for the cs and rd signals. if the load capacitance of the rd (read) signal line is greater than that of the cs (chip select) signal line, the deassertion timing of the read signal is delayed, which may lead to an unintentional extension of a read cycle. such an unintended read cycle extention, which is indicated as (a) in figure 3.6.2 may cause a problem. figure 3.6.2 delay read cycle of when the read signal is delayed example: when using an externally connected flash eeprom whose commands are compatible with the standard jedec commands, the toggle bit may not be read correctly. if the rising edge of the read signal in the cycle immediately preceding the flash eeprom access cycle does no t occur in time, a read cycle may be extended unintentilnally as indicated as indicated as (b) in figure 3.6.3. figure 3.6.3 flash eeprom toggle bit read cycle when the toggle bit is inverted due to this unexpected read cycle extension, the cpu read the toggle bit properly and it always reads the same value from the toggle bit. to avoid this situation, it is re commended to perform data polling. memory 1 chip select memory 2 chip select address clk (20 mhz) (a) rd address clk (20 mhz) flash eeprom chip select (b) toggle bit memory access toggle bit rd cycle 1 rd
tmp92cy23/cd23a 2009-08-28 92cy23-127 (2) the cautions at the time of the functional change of a csn . a chip select signal output has the ca se of a combination terminal with a general-purpose port function. in this case, an output latch register and a function control register are initialized by the reset action, and an object terminal is initialized by the port output (?1? or ?0?) by it. functional change although an object terminal is changed from a port to a chip sele ct signal output by setting up a function control register (pnfc register), the short pulse for several ns may be outputted to the changing timing. al though it does not become especially a problem when using the usual memory, it may become a problem when using a special memory. x x n+2 internal address bus function control signal pxx n n+2 a23 to a0 a port is set as csn . n output port csn internal signal external signal output pulse t ad3 * xx is a function register address.(when an output port is initialized by ?0?) the measure by software the countermeasures in s/w for avoiding this phenomenon are explained. since cs signal decodes the address of the access area and is generated, an unnecessary pulse is outputted by access to the object cs area immediately after setting it as a csn function. then, if internal area is accessed also immediately after setting a port as cs function, an unnecessary pulse will not output. 1. prohibition of use of an nmi function 2. the ban on interruption under functional change (di command) 3. a dummy command is added in order to carry out continuous internal access. 4. (access to a functional ch ange register is correspon ded by 16-bit command. (ldw command)) xx+1 n+2 internal address bus function control signal pxx n n+2 a23 to a0 a port is set as csn . xx output port csn internal signal external signal dummy access
tmp92cy23/cd23a 2009-08-28 92cy23-128 3.7 8-bit timers (tmra) the tmp92cy23/cd23a features 6 built-in 8-bit timers (tmra0-tmra5). these timers are paired into three modules: tmra01, tmra23 and tmra45. each module consists of two channels and can operate in any of the following four operating modes. ? 8-bit interval timer mode ? 16-bit interval timer mode ? 8-bit programmable square wave pulse generation output mode (ppg: variable duty cycl e with variable period) ? 8-bit pulse width modulation output mode (pwm: variable duty cycle with constant period) figure 3.7.1 to figure 3.7.3 show block diagrams fo r tmra01, tmra23 and tmra45. each chann e l consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. in addition, a timer flip-flop and a prescale r are provided for each pair of channels. the operation mode and timer flip-flops are cont rolled by a five-byte sfr (special function registers). each of the three modules (tmra01, tmra23 and tmra45) can be operated independently. all modules operate in the same manner; hence only the operation of tmra01 is explained here. table 3.7.1 registers and pins for each module module specification tmra01 tmra23 tmra45 input pin for external clock ta0in (shared with pc0) none none external pin output pin for timer flip-flop ta1out (shared with p80) ta3out (shared with p81) ta5out (shared with p83) timer run register ta01run (1100h) ta23run (1108h) ta45run (1110h) timer register ta0reg (1102h) ta1reg (1103h) ta2reg (110ah) ta3reg (110bh) ta4reg (1112h) ta5reg (1113h) timer mode register ta01mod(1104h) ta23mod(110ch) ta45mod(1114h) sfr (address) timer flip-flop control register ta1ffcr(1105h) ta3ffcr(110dh) ta5ffcr(1115h)
tmp92cy23/cd23a 2009-08-28 92cy23-129 3.7.1 block diagrams figure 3.7.1 tmra01 block diagram t1 t16 t256 8-bit comparator (cp1) 8-bit comparator (cp0) 8-bit up counter (uc0) 2 n over flow 8-bit up counter (uc1) timer flip-flop ta1ff match detect match detect 8-bit timer register ta1reg t1 t4 t16 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 run/clea r prescale r ta01mod prescale r clock: t0 ta01run selecto r 8-bit timer register ta0reg ta01mod ta01mod tmra0 interrupt output: intta0 tmra0 interrupt output: ta0trg ta01mod ta01run ta1ffcr timer flip-flop output: ta1out tmra1 interrupt output: intta1 internaldata bus ta01run ta01run selecto r internal data bus t a 0trg register buffer 0 external input clock: ta0in
tmp92cy23/cd23a 2009-08-28 92cy23-130 figure 3.7.2 tmra23 block diagram t1 t16 t256 8-bit comparator (cp3) 8-bit comparator (cp2) 8-bit up counter (uc2) 2 n over flow 8-bit up comparator (uc3) timer flip-flop ta3ff match detect match detect 8-bit timer register ta3reg t1 t4 t16 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 run/clea r prescale r ta23mod prescale r clock: t0 ta23run selecto r 8-bit timer register ta2reg ta23mod ta23mod tmra2 interrupt output: intta2 tmra2 interrupt output: ta2trg ta23mod ta23run ta3ffcr timer flip-flop output: ta3out tmra3 interrupt output: intta3 internal data bus ta23run ta23run selecto r internal data bus ta2trg register buffer 2
tmp92cy23/cd23a 2009-08-28 92cy23-131 figure 3.7.3 tmra45 block diagram t1 t16 t256 8-bit comparator (cp5) 8-bit comparator (cp4) 8-bit up counter (uc4) 2 n over- flow 8-bit up counter (uc5) timer flip-flop ta5ff match detect match detect 8-bit timer register ta5reg t1 t4 t16 512 256 128 64 32 16 8 4 2 t1 t4 t16 t256 run/clea r prescale r ta45mod prescale r clock: t0 ta45run selecto r 8-bit timer register ta4reg ta45mod ta45mod tmra4 interrupt output: intta4 tmra4 match output: ta4trg ta45mod ta45run ta5ffcr timer flip-flop output: ta5out tmra5 interrupt outptu: intta5 internal data bus ta45run ta45run selecto r internal data bus ta4trg register buffer 4
tmp92cy23/cd23a 2009-08-28 92cy23-132 3.7.2 operation of each circuit (1) prescalers a 9-bit prescaler generates the input clock to tmra01. the prescaler clock ( t0) is a divided clock (divided by 4) from the f fph. the prescaler?s operation can be controlled using ta01run in the timer control register. setting to ?1? starts the count; setting to ?0? clears the prescaler to ?0? and stops operation. table 3.7.2 shows the v ari ous p rescaler output clock resolutions. table 3.7.2 prescaler output clock resolution timer counter input clock tmra prescaler taxmod clock value syscr1 system clock syscr1 ? t1(1/2) t4(1/8) t16(1/32) t256(1/512) ? 1 (fs) fs/8 fs/32 fs/128 fs/2048 000 (1/1) fc/8 fc/32 fc/128 fc/2048 001 (1/2) fc/16 fc/64 fc/256 fc/4096 010 (1/4) fc/32 fc/128 fc/512 fc/8192 011 (1/8) fc/64 fc/256 fc/1024 fc/16384 100 (1/16) 0 (fc) 1/4 fc/128 fc/512 fc/2048 fc/32768 (2) up counters (uc0 and uc1) these are 8-bit binary counters which count up the input clock pulses for the clock specified by ta01mod. the input clock for uc0 is selectable and ca n be either the external clock input via the ta0in pin or one of the three internal clocks t1, t4 or t16. the clock setting is specified by the value set in ta01mod. the input clock for uc1 depends on the operation mode. in 16-bit timer mode, the overflow output from uc0 is used as the input clock. in any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks t1, t16 or t256, or the comparator output (the match detection signal) from tmra0. for each interval timer the timer operation control register bits ta01run and ta01run can be used to stop and clear the up counters and to control their count. a reset clears both up counters, stopping the timers.
tmp92cy23/cd23a 2009-08-28 92cy23-133 (3) timer registers (ta0reg and ta1reg) these are 8-bit registers, which can be used to set a time interval. when the value set in the timer register ta0reg or ta1reg matches the value in the corresponding up counter, the comparator match detect signal goes active. if the value set in the timer register is 00h, the signal goes active when the up counter overflows. the ta0reg has a double buffer structure, making a pair with the register buffer. the setting of the bit ta01run determines whether ta0reg?s double buffer structure is enabled or disabled. it is disabled if = ?0? and enabled if = ?1?. when the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2 n overflow occurs in pwm mode, or at the start of the ppg cycle in ppg mode. hence the double buffer cannot be used in timer mode. a reset initializes to ?0?, disabling the double buffer. to use the double buffer, write data to the timer register 0, set to ?1?, and write the following data to the re gister buffer. figure 3.7.4 show the configuration of ta0reg. figure 3.7.4 config uration of t a0reg note: the same memory address is allocated to the timer register and the register buffer. when = ?0?, the same value is written to the register buffer and the timer register; when = ?1?, only the register buffer is written to. the address of each timer register is as follows. ta0reg: 001102h ta1reg: 001103h ta2reg: 00110ah ta3reg: 00110bh ta4reg: 001112h ta5reg: 001113h all these registers are write only and cannot be read. internal data bus ta01run timer register a0 (ta0reg) register buffer 0 shift trigger b selector sa write write to ta0reg match detecting ppg cycle pwm 2 n overflow
tmp92cy23/cd23a 2009-08-28 92cy23-134 (4) comparator (cp0, cp1) the comparator compares the value in an up counter with the value set in a timer register. if they match, the up counter is cleared to ?0? and an interrupt signal (intta0 or intta1) is generated. if timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) timer flip-flop (ta1ff) the timer flip-flop (ta1ff) is a flip-flop inverted by the match detect signals (8-bit comparator output) of each interval timer. whether inversion is enabled or disabled is determined by the setting of the bit ta1ffcr in the timer flip-flops co ntrol register a reset clears the value of ta1ff to ?0?. writing ?01? or ?10? to ta1 ffcr sets ta1ff to ?0? or ?1?. writing ?00? to these bits inverts the value of ta1ff (this is known as software inversion). the ta1ff signal is output via the ta1out pin (which can also be used as p80). when this pin is used as the timer output, the timer flip-flop should be set beforehand using the port 8 function register p8cr and p8fc.
tmp92cy23/cd23a 2009-08-28 92cy23-135 3.7.3 sfr tmra01 run register 7 6 5 4 3 2 1 0 bit symbol ta0rde i2ta01 ta01prun ta1run ta0run ta01run (1100h) read/write r/w r/w reset state 0 0 0 0 0 tmra01 prescaler up counter (uc1) up counter (uc0) function double buffer 0: disable 1: enable idle2 0: stop 1: operate 0: stop and clear 1: run (count up) note: the values of bits 4 to 6 of ta01run are read as undefined values. tmra23 run register 7 6 5 4 3 2 1 0 bit symbol ta2rde i2ta23 ta23prun ta3run ta2run ta23run (1108h) read/write r/w r/w reset state 0 0 0 0 0 tmra23 prescaler up counter (uc3) up counter (uc2) function double buffer 0: disable 1: enable idle2 0: stop 1: operate 0: stop and clear 1: run (count up) note: the values of bits 4 to 6 of ta23run are read as undefined values. figure 3.7.5 register for tmra timer run/stop control 0 stop and clear 1 run (count up) ta0reg double buffer control 0 disable 1 enable timer run/stop control 0 stop and clear 1 run (count up) ta2reg double buffer control 0 disable 1 enable
tmp92cy23/cd23a 2009-08-28 92cy23-136 tmra45 run register 7 6 5 4 3 2 1 0 bit symbol ta4rde i2ta45 ta45prun ta5run ta4run ta45run (1110h) read/write r/w r/w reset state 0 0 0 0 0 tmra45 prescaler up counter (uc5) up counter (uc4) function double buffer 0: disable 1: enable idle4 0: stop 1: operate 0: stop and clear 1: run (count up) note: the values of bits 4 to 6 of ta45run are read as undefined values. figure 3.7.6 register for tmra timer run/stop control 0 stop and clear 1 run (count up) ta4reg double buffer control 0 disable 1 enable
tmp92cy23/cd23a 2009-08-28 92cy23-137 tmra01 mode register 7 6 5 4 3 2 1 0 bit symbol ta01m1 ta01m0 pwm01 pwm 00 ta1clk1 ta1clk0 ta0clk1 ta0clk0 ta01mod (1104h) read/write r/w reset state 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra1 00: ta0trg 01: t1 10: t16 11: t256 source clock for tmra0 00: ta0in pin input (note) 01: t1 10: t4 11: t16 00 ta0in (external input) 01 t1 10 t4 11 t16 ta01mod ?01? ta01mod = ?01? 00 matching output for tmra0 01 t1 10 t16 11 t256 overflow output from tmra0 (16-bit timer mode) 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock 00 8-bit timer 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra0), 8-bit timer (tmra1) note: when setting ta0in, set ta01mod after set port c0. figure 3.7.7 register for tmra pwm cycle selection tmra1 input clock tmra01 operation mode selection tmra0 input clock
tmp92cy23/cd23a 2009-08-28 92cy23-138 tmra23 mode register 7 6 5 4 3 2 1 0 bit symbol ta23m1 ta23m0 pwm21 pwm 20 ta3clk1 ta3clk0 ta2clk1 ta2clk0 ta23mod (110ch) read/write r/w reset state 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra3 00: ta2trg 01: t1 10: t16 11: t256 source clock for tmra2 00: reserved 01: t1 10: t4 11: t16 00 reserved 01 t1 10 t4 11 t16 ta23mod ?01? ta23mod = ?01? 00 matching output for tmra2 01 t1 10 t16 11 t256 overflow output from tmra2 (16-bit timer mode) 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock 00 8-bit timer 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra2), 8-bit timer (tmra3) figure 3.7.8 register for tmra pwm cycle selection tmra3 input clock tmra23 operation mode selection tmra2 input clock
tmp92cy23/cd23a 2009-08-28 92cy23-139 tmra45 mode register 7 6 5 4 3 2 1 0 bit symbol ta45m1 ta45m0 pwm41 pwm 40 ta5clk1 ta5clk0 ta4clk1 ta4clk0 ta45mod (1114h) read/write r/w reset state 0 0 0 0 0 0 0 0 function operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit ppg mode 11: 8-bit pwm mode pwm cycle 00: reserved 01: 2 6 10: 2 7 11: 2 8 source clock for tmra5 00: ta4trg 01: t1 10: t16 11: t256 source clock for tmra4 00: reserved 01: t1 10: t4 11: t16 00 reserved 01 t1 10 t4 11 t16 ta45mod ?01? ta45mod = ?01? 00 matching output for tmra4 01 t1 10 t16 11 t256 overflow output from tmra4 (16-bit timer mode) 00 reserved 01 2 6 source clock 10 2 7 source clock 11 2 8 source clock 00 8-bit timer 2ch 01 16-bit timer 10 8-bit ppg 11 8-bit pwm (tmra4), 8-bit timer (tmra5) figure 3.7.9 register for tmra pwm cycle selection tmra5 input clock tmra45 operation mode selection tmra4 input clock
tmp92cy23/cd23a 2009-08-28 92cy23-140 tmra1 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta1ffc1 ta1ffc0 ta1ffie ta1ffis ta1ffcr (1105h) read/write r/w reset state 1 1 0 0 a read-modify -write operation cannot be performed. function 00: invert ta1ff 01: set ta1ff 10: clear ta1ff 11: don?t care ta1ff control for inversion 0: disable 1: enable ta1ff inversion select 0: tmra0 1: tmra1 0 inversion by tmra0 ta1ffis 1 inversion by tmra1 0 disabled ta1ffie 1 enabled 00 inverts the value of ta1ff (software inversion) 01 sets ta1ff to ?1? 10 clears ta1ff to ?0? 11 don?t care note: the values of bits4 to 6 of ta1ffcr are read as undefined values. figure 3.7.10 register for tmra control of ta1ff inversion signal for timer flip-flop 1 (ta1ff) (don?t care except in 8-bit timer mode) inversion of ta1ff
tmp92cy23/cd23a 2009-08-28 92cy23-141 tmra3 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta3ffc1 ta3ffc0 ta3ffie ta3ffis ta3ffcr (110dh) read/write r/w reset state 1 1 0 0 a read-modify -write operation cannot be performed function 00: invert ta3ff 01: set ta3ff 10: clear ta3ff 11: don?t care ta3ff control for inversion 0: disable 1: enable ta3ff inversion select 0: tmra2 1: tmra3 0 inversion by tmra2 ta3ffis 1 inversion by tmra3 0 disabled ta3ffie 1 enabled 00 inverts the value of ta3ff (software inversion) 01 sets ta3ff to ?1? 10 clears ta3ff to ?0? 11 don?t care note: the values of bits4 to 6 of ta3ffcr are read as undefined values. figure 3.7.11 register for tmra control of ta3ff inversion signal for timer flip-flop 3 (ta3ff) (don?t care except in 8-bit timer mode) inversion of ta3ff
tmp92cy23/cd23a 2009-08-28 92cy23-142 tmra5 flip-flop control register 7 6 5 4 3 2 1 0 bit symbol ta5ffc1 ta5ffc0 ta5ffie ta5ffis ta5ffcr (1115h) read/write r/w reset state 1 1 0 0 a read-modify -write operation cannot be performed function 00: invert ta5ff 01: set ta5ff 10: clear ta5ff 11: don?t care ta5ff control for inversion 0: disable 1: enable ta5ff inversion select 0: tmra4 1: tmra5 0 inversion by tmra4 ta5ffis 1 inversion by tmra5 0 disabled ta5ffie 1 enabled 00 inverts the value of ta5ff (software inversion) 01 sets ta5ff to ?1? 10 clears ta5ff to ?0? 11 don?t care note: the values of bits4 to 6 of ta5ffcr are read as undefined values. figure 3.7.12 register for tmra control of ta5ff inversion signal for timer flip-flop 5 (ta5ff) (don?t care except in 8-bit timer mode) inversion of ta5ff
tmp92cy23/cd23a 2009-08-28 92cy23-143 tmra register 7 6 5 4 3 2 1 0 bit symbol ? read/write w ta0reg (1102h) reset state undefined bit symbol ? read/write w ta1reg (1103h) reset state undefined bit symbol ? read/write w ta2reg (110ah) reset state undefined bit symbol ? read/write w ta3reg (110bh) reset state undefined bit symbol ? read/write w ta4reg (1112h) reset state undefined bit symbol ? read/write w ta5reg (1113h) reset state undefined note: a read-modify -write operation cannot be performed. figure 3.7.13 register for tmra
tmp92cy23/cd23a 2009-08-28 92cy23-144 3.7.4 operation in each mode (1) 8-bit timer mode both tmra0 and tmra1 can be used indepe ndently as 8-bit interval timers. when set function and count data, tmra0 and tmra1 should be stopped. 1. generating interrupts at a fixed interval (using tmra1) to generate interrupts at constant intervals using tmra1 (intta1), first stop tmra1 then set the operation mode, input clock and a cycle to ta01mod and ta1reg register, respectively. then, enable the interrupt intta1 and start tmra1 counting. example: to generate an intta1 interrupt every 40 s at f c = 40 mhz, set each register as follows: *clock state: clock gear : 1/1(fc) msb lsb 7 6 5 4 3 2 1 0 ta01run ? x x x ? ? 0 ? stop tmra1 and clear it to ?0?. ta01mod 0 0 x x 0 1 ? ? select 8-bit timer mode and select t1 ( = (8/fc)s at f c = 40 mhz) as the input clock. ta1reg 1 1 0 0 1 0 0 0 set 40 s t1 = 200 = c8h to tareg. inteta01 x 1 0 1 ? ? ? ? enable intta1 and set it to level 5. ta01run ? x x x ? 11 ? start tmra1 counting. x: don?t care, ? : no change select the input clock using table 3.7.3. t able 3.7.3 selecting interrupt interval a nd the input clock using 8-bit timer input clock interrupt interval (at f c = 40 mhz) resolution t1 (8/fc) 0.2 s to 51.2 s 0.2 s t4 (32/fc) 0.8 s to 204.8 s 0.8 s t16 (128/fc) 3.2 s to 819.2 s 3.2 s t256 (2048/fc) 51.2 s to 13.11 ms 51.2 s note: the input clocks for tmra0 and tmra1 differ as follows: tmra0: uses tmra0 input (ta0in) and can be selected from t1, t4 or t16 tmra1: matches output of tmra0 (ta0trg) and can be selected from t1, t16, t256
tmp92cy23/cd23a 2009-08-28 92cy23-145 2. generating a 50 % duty ratio square wave pulse the state of the timer flip-flop (ta1ff) is inverted at constant intervals and its status output via the timer output pin (ta1out). example: to output a 1.2- s square wave pulse from the ta1out pin at f c = 40 mhz, use the following procedure to make the appropriate register settings. this example uses tmra1; however, either tmra0 or tmra1 may be used. *clock state: clock gear : 1/1(fc) 7 6 5 4 3 2 1 0 ta01run ? x x x ? ? 0 ? stop tmra1 and clear it to ?0?. ta01mod 0 0 x x 0 1 ? ? select 8-bit timer mode and select t1 ( = (8/fc)s at f c = 40 mhz) as the input clock. ta1reg 0 0 0 0 0 0 1 1 set the timer register to 1.2 s t1 2 = 3 ta1ffcr x x x x 1 0 1 1 clear ta1ff to ?0? and set it to invert on the match detect signal from tmra1. p8fc x x x x ? x ? 1 set p80 to function as the ta1out pin. ta01run ? x x x ? 11 ? start tmra1 counting. x: don?t care, ? : no change figure 3.7.14 square wave output timing chart (50 % duty) 0 1 2 3 0 1 2 3 0 1 2 3 0 t1 ta01run bit7 to bit2 bit1 bit0 up counter comparato r timing 0.6 s at f c = 40 mhz intta1 ta1ff ta1out comparator output (match detect) uc1 clea r
tmp92cy23/cd23a 2009-08-28 92cy23-146 3. making tmra1 count up on the match signal from the tmra0 comparator select 8-bit timer mode and set the comparator output from tmra0 to be the input clock to tmra1. figure 3.7.15 tmra1 count up on signal from tmra0 (2) 16-bit timer mode a 16-bit interval timer is configured by pairing the two 8-bit timers tmra0 and tmra1. to make a 16-bit interval timer in which tmra0 and tmra1 are cascaded together, set ta01mod to ?01?. in 16-bit timer mode, the overflow output from tmra0 is used as the input clock for tmra1, regardless of the value set in ta01mod. table 3.7.2 shows the re lati ons hip between the timer (interrupt) cycle and the input clock selection. to set the timer interrupt interval, set the lower eight bits in timer register ta0reg and the upper eight bits in ta1reg. be sure to set ta0reg first (as entering data in ta0reg temporarily disables the compare, while entering data in ta1reg starts the compare). setting example: to generate an intta1 interrupt every 0.2 s at f c = 40 mhz, set the timer registers ta0reg and ta1reg as follows: *clock state: clock gear : 1/1(fc) if t16 ( = (128/fc)s at f c = 40 mhz) is used as the input clock for counting, set the following value in the registers: 0.2 s (128/fc)s = 62500 = f424h; e.g. set ta1reg to f4h and ta0reg to 24h. 2 345 1 234 5 12 3 1 1 2 1 comparator output (tmra0 match) tmra0 up counter (when ta0reg = 5) tmra1 up counter (when ta1reg = 2) tmra1 match out p ut
tmp92cy23/cd23a 2009-08-28 92cy23-147 the comparator match signal is output from tmra0 each time the up counter uc0 matches ta0reg, though the up counter uc0 is not cleared. in the case of the tmra1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter uc1 and ta1reg match. when the match detect signal is output simultaneously from both the comparator tmra0 and tmra1, the up counters uc0 and uc1 are cleared to ?0? and the interrupt intta1 is generated. also, if inversion is enabled, the value of the timer flip-flop ta1ff is inverted. example: when ta1reg = 04h and ta0reg = 80h figure 3.7.16 timer output by 16-bit timer mode (3) 8-bit ppg (programmable pulse generation) output mode square wave pulses can be generated at any frequency and duty ratio by tmra0. the output pulses may be active low or active high. in this mode tmra1 cannot be used. tmra0 outputs pulses on the ta1out pin (which can also be used as p80). figure 3.7.17 8-bit ppg output waveforms inversion value of up counte r (uc1, uc0) tmra0 comparator match detect signal interru p t intta1 0080h 0180h 0280h 0380h 0480h timer out p ut ta1out tmra1 comparator match detect signal interru p t intta0 0080h t ta0reg ta1reg example: = ?01? ta0reg and uc0 match (interrupt intta0) ta1reg and uc0 match ( interru p t intta1 ) ta1out t h t l = ?10? t t l t h = ?01?
tmp92cy23/cd23a 2009-08-28 92cy23-148 in this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (uc0) matches the value in one of the timer registers ta0reg or ta1reg. the value set in ta0reg must be smaller than the value set in ta1reg. although the up counter for tmra1 (uc1) is not used in this mode, ta01run should be set to ?1? so that uc1 is set for counting. figure 3.7.18 shows a block diagram representing this mode. figure 3.7.18 block diag ra m of 8-bit ppg output mode if the ta0reg double buffer is enabled in this mode, the value of the register buffer will be shifted into ta0reg each time ta1reg matches uc0. use of the double buffer facilitates the handling of low duty waves (when duty is varied). figure 3.7.19 operation of register buffer 0 q 2 q 1 match with ta0reg and up counter match with ta1reg q 3 q 2 (up counter = q 1 ) (up counter = q 2 ) shift from register buffer 0 ta0reg (register buffer 0) write ta0reg (value to be compared) register buffe r 8-bit up counter (uc0) comparator comparator ta0in t1 t4 t16 ta01mod ta1ff ta0reg register buffer 0 ta1reg ta01run ta0reg-wr ta01run ta1out ta1ffcr intta0 intta1 shift trigge r internal data bus selecto r inversion selecto r
tmp92cy23/cd23a 2009-08-28 92cy23-149 example: to generate 1/4 duty 62.5 khz pulses (at f c = 40 mhz) *clock state: clock gear : 1/1(fc) calculate the value that should be set in the timer register. to obtain a frequency of 62.5 khz, the pulse cycle t should be: t = 1/62.5 khz = 16 s t1 (= (8/fc)s @f c = 40 mhz); 16 s (8/fc)s = 80 therefore set ta1reg = 80 = 50h the duty is to be set to 1/4: t 1/4 = 16 s 1/4 = 4 s 4 s (8/fc)s = 20 therefore, set ta0reg = 20 = 14h 7 6 5 4 3210 ta01run 0 x x x ? 0 0 0 stop tmra0 and tmra1 and clear it to ?0?. ta01mod 1 0 x x x x 0 1 set the 8-bit ppg mode, and select t1 as input clock. ta0reg 0 0 0 1 0100 write 14h. ta1reg 0 1 0 1 0000 write 50h. ta1ffcr x x x x 0 1 1 x set ta1ff, enabling both inversion and the double buffer. 10 generate a negative logic pulse. p8fc2 x x x x ? x ? 1 set p80 as the ta1out pin. ta01run 1 x x x ? 1 1 1 start tmra0 and tmra1 counting. x: don't care, ? : no change 16 s
tmp92cy23/cd23a 2009-08-28 92cy23-150 (4) 8-bit pwm output mode this mode is only valid for tmra0. in this mode, a pwm pulse with the maximum resolution of 8 bits can be output. when tmra0 is used the pwm pulse is output on the ta1out pin (which is also used as p80). tmra1 can also be used as an 8-bit timer. the timer output is inverted when the up counter (uc0) matches the value set in the timer register ta0reg or when 2 n counter overflow occurs (n = 6, 7 or 8 as specified by ta01mod). the up counter uc0 is cleared when 2 n counter overflow occurs. the following conditions must be sa tisfied before this pwm mode can be used. value set in ta0reg < value set for 2 n counter overflow value set in ta0reg ?0? figure 3.7.20 8-bit pwm waveforms figure 3.7.21 shows a block diagram representing this mode. figure 3.7.21 block diag ra m of 8-bit pwm mode ta0reg and uc0 match ta1out t pwm (pwm cycle) 2 n overflow (intta0 interrupt) selector 8-bit up counter (uc0) comparator ta0in t1 t4 t16 ta01mod ta1ff ta0reg register buffer 0 selector ta01run ta0reg-wr ta01run ta1out ta1ffcr shift trigge r internal data bus clear 2 n overflow control intta0 ta01mod overflow inversion
tmp92cy23/cd23a 2009-08-28 92cy23-151 in this mode the value of the register buffer will be shifted into ta0reg if 2 n overflow is detected when the ta0reg double buffer is enabled. use of the double buffer facilitates th e handling of low duty ratio waves. figure 3.7.22 register buffer operation example: to output the following pwm waves on the ta1out pin (at f c = 40 mhz). *clock state: clock gear : 1/1(fc) to achieve a 25.6- s pwm cycle by setting t1 ( = (8/fc)s at f c = 40 mhz): 25.6 s (8/fc)s = 128 = 2 n therefore n should be set to 7. since the low level period is 18.0 s when t1 = (8/fc)s, set the following value for treg0: 18.0 s (8/fc)s = 90 = 5ah msb lsb 7 6 5 4 3210 ta01run ? x x x ? ? ? 0 stop tmra0 and clear it to ?0? ta01mod 1 1 1 0 ? ? 0 1 select 8-bit pwm mode (cycle: 2 7 ) and select t1 as the input clock. ta0reg 0 1 0 1 1010 write 5ah. ta1ffcr x x x x 1 0 1 x clear ta1ff to ?0?, enable the inversion and double buffer. p8fc2 ? ? ? ? ? ? ? 1 set p80 as the ta1out pin. ta01run 1 x x x ? 1 ? 1 start tmra0 counting. x: don't care, ? : no change 18.0 s 25.6 s q 2 q 1 match with ta0reg q 3 q 2 up counter = q 1 up counter = q 2 shift into ta0reg ta0reg (register buffer 0) write ta0reg (value to be compared) re g ister buffe r 2 n overflow
tmp92cy23/cd23a 2009-08-28 92cy23-152 table 3.7.4 pwm cycle pwm cycle taxxmod 2 6 (x64) 2 7 (x128) 2 8 (x256) taxxmod taxxmod taxxmod clock gear value syscr1 system clock syscr0 ? t1(x2) t4(x8) t16(x32) t1(x2) t4(x8) t16(x32) t1(x2) t4(x8) t16(x32) ? 1(fs) 512/fs 2048/fs 8192/fs 1024/fs 4096/ fs 16384/fs 2048/fs 8192/fs 32768/fs 000(x1) 512/fc 2048/fc 8192/fc 1024/fc 4096/ fc 16384/fc 2048/fc 8192/fc 32768/fc 001(x2) 1024/fc 4096/fc 16384/fc 2048/fc 8192/ fc 32768/fc 4096/fc 16384/fc 65536/fc 010(x4) 2048/fc 8192/fc 32768/fc 4096/fc 16384 /fc 65536/fc 8192/fc 32768/fc 131072/fc 011(x8) 4096/fc 16384/fc 65536/fc 8192/fc 32768 /fc 131072/fc 16384/fc 65536/fc 262144/fc 100(x16) 0(fc) 4 8192/fc 32768/fc 131072/fc 16384/fc 65536/fc 262144/fc 32768/fc 131072/fc 524288/fc (5) settings for each mode table 3.7.5 shows the sfr settings for each mode. t able 3.7.5 t i mer mode setting registers register name ta01mod ta1ffcr function timer mode pwm cycle upper timer input clock lower timer input clock timer f/f invert signal select 8-bit timer 2 channels 00 ? lower timer match, t1, t16, t256 (00, 01, 10, 11) external clock, t1, t4, t16 (00, 01, 10, 11) 0: lower timer output 1: upper timer output 16-bit timer mode 01 ? ? external clock, t1, t4, t16 (00, 01, 10, 11) ? 8-bit ppg 1 channel 10 ? ? external clock, t1, t4, t16 (00, 01, 10, 11) ? 8-bit pwm 1 channel 11 2 6 , 2 7 , 2 8 (01, 10, 11) ? external clock, t1, t4, t16 (00, 01, 10, 11) ? 8-bit timer 1 channel 11 ? t1, t16, t256 (01, 10, 11) ? output disabled ? : don?t care
tmp92cy23/cd23a 2009-08-28 92cy23-153 3.8 16-bit timer/event counters (tmrb0) the tmp92cy23/cd23a incorporates two multifunctional 16-bit timer/event counter (tmrb0 and tmrb1) which has the following operation modes: ? 16-bit interval timer ? 16-bit event counter ? 16-bit programmable pulse generation (ppg) can be used following operation modes by capture function. ? frequency measurement mode ? pulse width measurement mode ? time differential measurement mode figure 3.8.1 and figure 3.8.2 show block diag ram of tmrb0 and tmrb1. t he tim e r/event counter consists of a 16-bit up counter, two 16-bit timer registers (one of them with a double buffer structure), two 16-bit capture register, two comparators, a capture input controller, a timer flip -flop and a control circuit. the timer/event counter is controlled by a 11-byte sfr. each channel(tmrb0,tmrb1) operate independently. in this section, the explanation describes only for tmrb1 because each channel is identical operation except for the difference as follows; table 3.8.1 pins and sfr of tmrb channel spec tmrb0 tmrb1 external clock/ caputre triggr input pin none tb1in0 (share with pd1) tb1in1 (share with pd2) external pin timer flip-flop output pin tb0out0 (share with pd0) tb1out0 (share with pd3) tb1out1 (share with pd4) timre run register tb0run (1180h) tb1run (1190h) timrer mode register tb0mod (1182h) tb1mod (1192h) timre flip-flop control register tb0ffcr (1183h) tb1ffcr (1193h) tb0rg0l (1188h) tb1rg0l (1198h) tb0rg0h (1189h) tb1rg0h (1199h) tb0rg1l (118ah) tb1rg1l (119ah) timer register tb0rg1h (118bh) tb1rg1h (119bh) tb0cp0l (118ch) tb1cp0l (119ch) tb0cp0h (118dh) tb1cp0h (119dh) tb0cp1l (118eh) tb1cp1l (119eh) sfr (address) capture register tb0cp1h (118fh) tb1cp1h (119fh)
tmp92cy23/cd23a 2009-08-28 92cy23-154 3.8.1 block diagrams figure 3.8.1 block diagram of tmrb0 internal data bus slelector 16-bit comparator (cp10) tb0mod t1 t4 t16 timer flip-flop control tb0ff0 tb0out0 match detection 16-bit timer register tb0rg0h/l register buffer 10 ta1out tb1mod 16-bit time register tb0rg1h/l tb0mod 16-bit comparator (cp11) capture, external interrupt input control tb0run caputure register 1 tb0cp1h/l capture register 0 tb0cp0h/l run/ clear internal data bus match detection 16-bit up counter (uc10) count clock (from tmra01 ) prescaler clock: t0 32 16 8 4 2 t1 t4 t16 tb0run internal data bus tb0mod intenal data bus overflow interrupt inttbof0 time r flip-flop timer flip-flop output inter r upt output inttb00 inttb01 tb0run
tmp92cy23/cd23a 2009-08-28 92cy23-155 figure 3.8.2 block diagram of tmrb1 internal data bus slelector 16-bit comparator (cp12) tb1mod t1 t4 t16 timer flip-flop control tb1ff0 tb1out0 match detection 16-bit timer register tb1rg0h/l register buffer 12 ta3out tb1in0 tb1in1 tb1mod 16-bit time register tb1rg1h/l tb1mod 16-bit comparator (cp13) capture, external interrupt input control tb1run caputure register 1 tb1cp1h/l capture register 0 tb1cp0h/l run/ clear internal data bus match detection 16-bit up counter (uc12) count clock (from tmra23 ) prescaler clock: t0 32 16 8 4 2 t1 t4 t16 tb1run internal data bus tb1mod intenal data bus overflow interrupt inttbof1 time r flip-flop timer flip-flop output interrupt output inttb10 inttb11 tb1run tb1ff1 tb1out1 external interrupt input int5 int6
tmp92cy23/cd23a 2009-08-28 92cy23-156 3.8.2 operation of each block (1) prescaler the 5-bit prescaler generates the source clock for tmrb1. the prescaler clock ( t0) is a divided clock (divided by 4) from the f fph. this prescaler can be started or stopped using tb1run. counting starts when is set to ?1?; the prescaler is cleared to ?0? and stops operation when is cleared to ?0?. table 3.8.2 prescaler clock resolution timer counter input clock tmrb prescaler tbxmod gear value syscr1 system clock syscr1 ? t1(1/2) t4(1/8) t16(1/32) ? 1 (fs) fs/8 fs/32 fs/128 000 (1/1) fc/8 fc/32 fc/128 001 (1/2) fc/16 fc/64 fc/256 010 (1/4) fc/64 fc/128 fc/512 011 (1/8) fc/64 fc/256 fc/1024 100 (1/16) 0 (fc) 1/4 fc/128 fc/512 fc/2048 (2) up counter (uc12) uc12 is a 16-bit binary counter which counts up pulses input from the clock specified by tb0mod. any one of the prescaler internal clocks t1, t4 and t16 can be selected as the input clock. counting or stopping and clearing of the counter is controlled by tb1run. tmrb0 cannot choose an external clock as an input clock (there is no external clock input terminal). when clearing is enabled, the up counter uc12 will be cleared to 0 each time its value matches the value in the timer register tb1rg1h/l. if clearing is disabled, the counter operates as a free-running counter. clearing can be enable d or disabled using tb1mod. a timer overflow interrupt (inttbof1) is generated when uc12 overflow occurs.
tmp92cy23/cd23a 2009-08-28 92cy23-157 (3) timer registers (tb1rg 0h/l and tb1rg1h/l) these 16-bit registers are used to set the interval time. when the value in the up counter uc12 matches the value set in th is timer register, the comparator match detect signal will go active. setting data for both upper and lower timer registers is always needed. for example, either using a 2-byte data transfer instruction or using a 1-byte data transfer instruction twice for the lower 8 bits and upper 8 bits in order. the tb1rg0h/l timer register has a double-b uffer structure, which is paired with a register buffer. the value set in tb1run determines whether the double-buffer structure is enabled or di sabled: it is disabled when = ?0?, and enabled when = ?1?. when the double buffer is enabled, data is transferred from the register buffer to the timer register when the values in the up counter (uc12) and the timer register tb1rg1h/l match. after a reset, tb1rg0h/l and tb1rg1h/l are undefined. if the 16-bit timer is to be used after a reset, data should be written to it beforehand. on a reset is initialized to ?0?, disabling the double buffer. to use the double buffer, write data to the timer register , set to ?1?, then write data to the register buffer as shown below. tb1rg0h/l and the register buffer both have the same memory addresses (1188h and 1189h) allocated to them. if = ?0?, the value is written to both the timer register and the register buffer. if = ?1?, the value is written to the register buffer only. the addresses of the timer registers are as follows: the timer registers are write-only registers and thus cannot be read. tmrb0 1189h 1188h 118bh 118ah tb0rg0h/l tb0rg1h/l upper 8 bits (tb0rg0h) lower 8 bits (tb0rg0l) upper 8 bits (tb0rg1h) lower 8 bits (tb0rg1l) tmrb1 1199h 1198h 119bh 119ah tb1rg0h/l tb1rg1h/l upper 8 bits (tb1rg0h) lower 8 bits (tb1rg0l) upper 8 bits (tb1rg1h) lower 8 bits (tb1rg1l)
tmp92cy23/cd23a 2009-08-28 92cy23-158 (4) capture registers (tb1cp 0h/l and tb1cp1h/l) these 16-bit registers are used to latch the values in the up counters uc12. all 16 bits of data in the capture registers should be read. for example, using a 2-byte data load instruction or two 1-byte data load instructions twice for lower 8 bits and upper 8 bits in order. the addresses of the capture registers are as follows: the capture registers are read-only r egisters and thus cannot be written to. (5) capture input control this circuit controls the timing to latch the value of the up counter uc12 into tb1cp0h/l and tb1cp1h/l. interrupt timing of capture register and se lection edge of external interrupt are set by tb1mod

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